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-rw-r--r--src/southbridge/intel/bd82x6x/early_rcba.c2
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c4
-rw-r--r--src/southbridge/intel/common/spi.c22
-rw-r--r--src/southbridge/intel/i82801ix/sata.c4
-rw-r--r--src/southbridge/intel/i82801jx/sata.c4
-rw-r--r--src/southbridge/intel/ibexpeak/setup_heci_uma.c4
6 files changed, 20 insertions, 20 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index 49c137aec1..9daf4971d2 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -76,7 +76,7 @@ void southbridge_configure_default_intmap(void)
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ (void)RCBA16(OIC);
}
void southbridge_rcba_config(void)
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index e243c9782c..9dc58fdced 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -142,8 +142,8 @@ static void sata_init(struct device *dev)
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ (void)read32(abar + 0x0c); /* Read back 1 */
+ (void)read32(abar + 0x0c); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
reg32 = read32(abar + 0x24);
reg32 &= ~0x00000002;
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 44d283c590..1d274e8f0d 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -158,7 +158,7 @@ static u8 readb_(const void *addr)
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned int) addr & 0xffff) - 0xf020);
+ v, ((unsigned int)addr & 0xffff) - 0xf020);
return v;
}
@@ -167,7 +167,7 @@ static u16 readw_(const void *addr)
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned int) addr & 0xffff) - 0xf020);
+ v, ((unsigned int)addr & 0xffff) - 0xf020);
return v;
}
@@ -176,7 +176,7 @@ static u32 readl_(const void *addr)
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned int) addr & 0xffff) - 0xf020);
+ v, ((unsigned int)addr & 0xffff) - 0xf020);
return v;
}
@@ -184,21 +184,21 @@ static void writeb_(u8 b, void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned int) addr & 0xffff) - 0xf020);
+ b, ((unsigned int)addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned int) addr & 0xffff) - 0xf020);
+ b, ((unsigned int)addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, void *addr)
{
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned int) addr & 0xffff) - 0xf020);
+ b, ((unsigned int)addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@@ -787,8 +787,8 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to read %x-%x which is out of chip\n",
- (unsigned int) addr,
- (unsigned int) addr+(unsigned int) len);
+ (unsigned int)addr,
+ (unsigned int)addr+(unsigned int) len);
return -1;
}
@@ -835,7 +835,7 @@ static void ich_fill_data(const uint8_t *data, int len)
if ((i % 4) == 0)
temp32 = 0;
- temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
+ temp32 |= ((uint32_t)data[i]) << ((i % 4) * 8);
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
writel_(temp32, cntlr.data + (i - (i % 4)));
@@ -856,7 +856,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to write 0x%x-0x%x which is out of chip\n",
- (unsigned int)addr, (unsigned int) (addr+len));
+ (unsigned int)addr, (unsigned int)(addr+len));
return -1;
}
@@ -890,7 +890,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
len -= block_len;
}
printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
- (unsigned int) (addr - start), start);
+ (unsigned int)(addr - start), start);
return 0;
}
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 260d76a8cb..7621a4d4b9 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -46,8 +46,8 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
/* PI (Ports implemented) */
write32(abar + 0x0c, port_map);
/* PCH code reads back twice, do we need it, too? */
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ (void)read32(abar + 0x0c); /* Read back 1 */
+ (void)read32(abar + 0x0c); /* Read back 2 */
/* VSP (Vendor Specific Register) */
reg32 = read32(abar + 0xa0);
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c
index 4e014817c9..1694d3caf0 100644
--- a/src/southbridge/intel/i82801jx/sata.c
+++ b/src/southbridge/intel/i82801jx/sata.c
@@ -45,8 +45,8 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map)
/* PI (Ports implemented) */
write32(abar + 0x0c, port_map);
/* PCH code reads back twice, do we need it, too? */
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ (void)read32(abar + 0x0c); /* Read back 1 */
+ (void)read32(abar + 0x0c); /* Read back 2 */
/* VSP (Vendor Specific Register) */
reg32 = read32(abar + 0xa0);
diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
index e490573812..572e5e7a76 100644
--- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
@@ -97,7 +97,7 @@ static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_si
csr.raw = read32(DEFAULT_HECIBAR + 0xc);
} while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
- *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
+ *(u32 *)head = read32(DEFAULT_HECIBAR + 0x8);
if (!head->length) {
write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
*packet_size = 0;
@@ -188,7 +188,7 @@ static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int he
};
u32 reply_size;
- send_heci_message((u8 *) &msg, sizeof(msg), 0, 7);
+ send_heci_message((u8 *)&msg, sizeof(msg), 0, 7);
reply_size = sizeof(reply);
if (recv_heci_message(&reply, &reply_size) == -1)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 23:13:07 +0000