diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/broadcom/bcm5785/bcm5785.h | 7 | ||||
| -rw-r--r-- | src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ax/i82801ax_smbus.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801bx/i82801bx_smbus.h | 68 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55.h | 5 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c | 3 | ||||
| -rw-r--r-- | src/southbridge/sis/sis966/sis966_early_setup_car.c | 2 | ||||
| -rw-r--r-- | src/southbridge/sis/sis966/sis966_early_smbus.c | 172 | ||||
| -rw-r--r-- | src/southbridge/sis/sis966/sis966_smbus.h | 168 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_early_car.c | 4 |
10 files changed, 265 insertions, 175 deletions
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index 5f7f94f5e2..c06a961ffd 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -3,6 +3,13 @@ #include "chip.h" +#ifndef __PRE_RAM__ void bcm5785_enable(device_t dev); +#else +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif + +void ldtstop_sb(void); +unsigned get_sbdn(unsigned bus); #endif /* BCM5785_H */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c index 62e004dac3..41b4ca3a10 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c @@ -4,6 +4,7 @@ */ #include <reset.h> +#include "bcm5785.h" #include "bcm5785_enable_rom.c" static void bcm5785_enable_lpc(void) @@ -53,12 +54,12 @@ static void bcm5785_enable_wdt_port_cf9(void) pci_write_config8(dev, 0x40, (1<<2)); } -static unsigned get_sbdn(unsigned bus) +unsigned get_sbdn(unsigned bus) { device_t dev; /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. + * There can only be one bcm5785 on a hypertransport chain/bus. */ dev = pci_locate_device_on_bus( PCI_ID(0x1166, 0x0036), @@ -70,7 +71,7 @@ static unsigned get_sbdn(unsigned bus) #define SB_VFSMAF 0 -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { //ACPI Decode Enable outb(0x0e, 0xcd6); @@ -89,7 +90,7 @@ static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) outb(9, 0xcd7); } -static void ldtstop_sb(void) +void ldtstop_sb(void) { outb(1, 0x2060); } diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h index 06d987721f..d3f49f9a71 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_smbus.h +++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.h @@ -113,8 +113,6 @@ static int do_smbus_read_byte(unsigned device, unsigned address) static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { - unsigned char global_control_register; - unsigned char global_status_register; unsigned char byte; unsigned char stat; int i; diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h index 5586ac752c..a873958833 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -51,6 +51,7 @@ static int smbus_wait_until_done(void) return loops ? 0 : -1; } +#ifdef UNUNSED_CODE static int smbus_wait_until_blk_done(void) { unsigned loops = SMBUS_TIMEOUT; @@ -63,6 +64,7 @@ static int smbus_wait_until_blk_done(void) } while ((byte & (1 << 7)) == 0); return loops ? 0 : -1; } +#endif static int do_smbus_read_byte(unsigned device, unsigned address) { @@ -110,3 +112,69 @@ static int do_smbus_read_byte(unsigned device, unsigned address) return byte; } +#ifdef UNUNSED_CODE +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ + unsigned char byte; + unsigned char stat; + int i; + + print_err("Untested smbus_write_block called\n"); + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66); + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done() < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\n"); + return 0; +} +#endif diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 2f6e9d284f..687232f302 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -24,6 +24,9 @@ #include "chip.h" +#ifndef __PRE_RAM__ void mcp55_enable(device_t dev); - +#else +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); +#endif #endif /* MCP55_H */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c b/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c index 3b5a507538..5c5f07c81a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c @@ -20,6 +20,7 @@ */ #include <reset.h> +#include "mcp55.h" static unsigned get_sbdn(unsigned bus) { @@ -52,7 +53,7 @@ void hard_reset(void) outb(0x0e, 0x0cf9); } -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { /* default value for mcp55 is good */ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ diff --git a/src/southbridge/sis/sis966/sis966_early_setup_car.c b/src/southbridge/sis/sis966/sis966_early_setup_car.c index 2f7569ee3b..9de33137a7 100644 --- a/src/southbridge/sis/sis966/sis966_early_setup_car.c +++ b/src/southbridge/sis/sis966/sis966_early_setup_car.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) +void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { uint32_t tgio_ctrl; uint32_t pll_ctrl; diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/sis966_early_smbus.c index 3d4954b64f..1c81bf16fd 100644 --- a/src/southbridge/sis/sis966/sis966_early_smbus.c +++ b/src/southbridge/sis/sis966/sis966_early_smbus.c @@ -23,6 +23,174 @@ #define SMBUS0_IO_BASE 0x8D0 +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { + return 0; + } + outb(val,smbus_io_base + SMBHSTSTAT); + } while(--loops); + return -2; +} + +int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(smbus_io_base + 0x00); + if ( (val & 0xff) != 0x02) { + return 0; + } + } while(--loops); + return -3; +} + +int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +{ + unsigned char global_status_register; + unsigned char byte; + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; +} + +int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +{ + unsigned global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + +static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + outb(0xff, smbus_io_base + 0x00); + smbus_delay(); + outb(0x20, smbus_io_base + 0x03); + smbus_delay(); + + outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); + smbus_delay(); + outb(address & 0xff, smbus_io_base + 0x05); + smbus_delay(); + outb(0x12, smbus_io_base + 0x03); + smbus_delay(); + +int i,j; +for(i=0;i<0x1000;i++) +{ + if (inb(smbus_io_base + 0x00) != 0x08) + { smbus_delay(); + for(j=0;j<0xFFFF;j++); + } +}; + + global_status_register = inb(smbus_io_base + 0x00); + byte = inb(smbus_io_base + 0x08); + + if (global_status_register != 0x08) { // lose check, otherwise it should be 0 + print_debug("Fail");print_debug("\r\t"); + return -1; + } + print_debug("Success");print_debug("\r\t"); + return byte; +} + + +static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +{ + unsigned global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + + + static const uint8_t SiS_LPC_init[34][3]={ {0x04, 0xF8, 0x07}, //Reg 0x04 {0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash @@ -564,11 +732,11 @@ static void enable_smbus(void) printk(BIOS_DEBUG, "enable_smbus <--------\n"); } -static int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); } diff --git a/src/southbridge/sis/sis966/sis966_smbus.h b/src/southbridge/sis/sis966/sis966_smbus.h index 3294be5899..087ea47f23 100644 --- a/src/southbridge/sis/sis966/sis966_smbus.h +++ b/src/southbridge/sis/sis966/sis966_smbus.h @@ -37,166 +37,10 @@ */ #define SMBUS_TIMEOUT (100*1000*10) -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { - return 0; - } - outb(val,smbus_io_base + SMBHSTSTAT); - } while(--loops); - return -2; -} - -static int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(smbus_io_base + 0x00); - if ( (val & 0xff) != 0x02) { - return 0; - } - } while(--loops); - return -3; -} -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned char global_status_register; - unsigned char byte; - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; -} -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - outb(0xff, smbus_io_base + 0x00); - smbus_delay(); - outb(0x20, smbus_io_base + 0x03); - smbus_delay(); - - outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); - smbus_delay(); - outb(address & 0xff, smbus_io_base + 0x05); - smbus_delay(); - outb(0x12, smbus_io_base + 0x03); - smbus_delay(); - -int i,j; -for(i=0;i<0x1000;i++) -{ - if (inb(smbus_io_base + 0x00) != 0x08) - { smbus_delay(); - for(j=0;j<0xFFFF;j++); - } -}; - - global_status_register = inb(smbus_io_base + 0x00); - byte = inb(smbus_io_base + 0x08); - - if (global_status_register != 0x08) { // lose check, otherwise it should be 0 - print_debug("Fail");print_debug("\r\t"); - return -1; - } - print_debug("Success");print_debug("\r\t"); - return byte; -} - - -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} +int smbus_wait_until_ready(unsigned smbus_io_base); +int smbus_wait_until_done(unsigned smbus_io_base); +int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device); +int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val); +int smbus_read_byte(unsigned device, unsigned address); +int smbus_write_byte(unsigned device, unsigned address, unsigned char val); diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c index 037f5a75eb..aa224a9469 100644 --- a/src/southbridge/via/k8t890/k8t890_early_car.c +++ b/src/southbridge/via/k8t890/k8t890_early_car.c @@ -113,7 +113,7 @@ u8 k8t890_early_setup_ht(void) return 1; } -static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); @@ -134,7 +134,7 @@ static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) return nvram_pos; } -static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { switch (size) { case 1: |