diff options
Diffstat (limited to 'src/southbridge')
24 files changed, 173 insertions, 134 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 6b8d654a18..f95a0b46a0 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -198,7 +200,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -209,7 +211,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -224,7 +226,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -254,7 +256,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -262,7 +264,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -285,7 +287,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -296,13 +298,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -312,7 +314,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -323,7 +325,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -349,20 +351,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index e71fedae91..51fc7bb1f4 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -15,6 +15,7 @@ */ #include <stdint.h> +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -150,7 +151,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 7b42b0680f..8bd3b961b7 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -17,6 +17,7 @@ #define INTEL_COMMON_GPIO_H #include <stdint.h> +#include <compiler.h> /* LPC GPIO Base Address Register */ #define GPIO_BASE 0x48 @@ -91,7 +92,7 @@ struct pch_gpio_set1 { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set2 { u32 gpio32 : 1; @@ -126,7 +127,7 @@ struct pch_gpio_set2 { u32 gpio61 : 1; u32 gpio62 : 1; u32 gpio63 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set3 { u32 gpio64 : 1; @@ -141,7 +142,7 @@ struct pch_gpio_set3 { u32 gpio73 : 1; u32 gpio74 : 1; u32 gpio75 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_map { struct { diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 13db224a97..4b9bd20b2d 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <compiler.h> #include <bootstate.h> #include <commonlib/helpers.h> #include <delay.h> @@ -82,7 +83,7 @@ typedef struct ich7_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; +} __packed ich7_spi_regs; typedef struct ich9_spi_regs { uint32_t bfpr; @@ -115,7 +116,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/southbridge/intel/fsp_bd82x6x/gpio.h b/src/southbridge/intel/fsp_bd82x6x/gpio.h index d2f0e50452..3279be8ee5 100644 --- a/src/southbridge/intel/fsp_bd82x6x/gpio.h +++ b/src/southbridge/intel/fsp_bd82x6x/gpio.h @@ -17,6 +17,8 @@ #ifndef INTEL_BD82X6X_GPIO_H #define INTEL_BD82X6X_GPIO_H +#include <compiler.h> + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -69,7 +71,7 @@ struct pch_gpio_set1 { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set2 { u32 gpio32 : 1; @@ -104,7 +106,7 @@ struct pch_gpio_set2 { u32 gpio61 : 1; u32 gpio62 : 1; u32 gpio63 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set3 { u32 gpio64 : 1; @@ -120,7 +122,7 @@ struct pch_gpio_set3 { u32 gpio74 : 1; u32 gpio75 : 1; u32 fill_bitfield : 20; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_map { union { diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h index 6b8d654a18..f95a0b46a0 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.h +++ b/src/southbridge/intel/fsp_bd82x6x/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -198,7 +200,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -209,7 +211,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -224,7 +226,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -254,7 +256,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -262,7 +264,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -285,7 +287,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -296,13 +298,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -312,7 +314,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -323,7 +325,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -349,20 +351,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 83bc832733..fc843194a7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -146,7 +147,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/fsp_i89xx/gpio.h b/src/southbridge/intel/fsp_i89xx/gpio.h index ee5484d26b..b89ab3ed37 100644 --- a/src/southbridge/intel/fsp_i89xx/gpio.h +++ b/src/southbridge/intel/fsp_i89xx/gpio.h @@ -17,6 +17,8 @@ #ifndef INTEL_I89XX_GPIO_H #define INTEL_I89XX_GPIO_H +#include <compiler.h> + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -69,7 +71,7 @@ struct pch_gpio_set1 { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set2 { u32 gpio32 : 1; @@ -104,7 +106,7 @@ struct pch_gpio_set2 { u32 gpio61 : 1; u32 gpio62 : 1; u32 gpio63 : 1; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_set3 { u32 gpio64 : 1; @@ -120,7 +122,7 @@ struct pch_gpio_set3 { u32 gpio74 : 1; u32 gpio75 : 1; u32 fill_bitfield : 20; -} __attribute__ ((packed)); +} __packed; struct pch_gpio_map { union { diff --git a/src/southbridge/intel/fsp_i89xx/me.h b/src/southbridge/intel/fsp_i89xx/me.h index 6b8d654a18..f95a0b46a0 100644 --- a/src/southbridge/intel/fsp_i89xx/me.h +++ b/src/southbridge/intel/fsp_i89xx/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -198,7 +200,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -209,7 +211,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -224,7 +226,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -254,7 +256,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -262,7 +264,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -285,7 +287,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -296,13 +298,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -312,7 +314,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -323,7 +325,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -349,20 +351,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h index 83bc832733..fc843194a7 100644 --- a/src/southbridge/intel/fsp_i89xx/nvs.h +++ b/src/southbridge/intel/fsp_i89xx/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -146,7 +147,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h index 8a0b578fe0..d8fbcb985d 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.h +++ b/src/southbridge/intel/fsp_rangeley/gpio.h @@ -17,6 +17,8 @@ #ifndef INTEL_RANGELEY_GPIO_H #define INTEL_RANGELEY_GPIO_H +#include <compiler.h> + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -72,14 +74,14 @@ struct soc_gpio { u32 gpio29 : 1; u32 gpio30 : 1; u32 gpio31 : 1; -} __attribute__ ((packed)); +} __packed; struct soc_cfio { u32 pad_conf_0; u32 pad_conf_1; u32 pad_val; u32 pad_dft; -} __attribute__ ((packed)); +} __packed; struct soc_gpio_map { /* GPIO core */ diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index 5449f9457f..fd3329051d 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -143,7 +145,7 @@ typedef struct { u8 mmio; /* 0xf4 - 64bit mmio support */ u8 rsvd13[11]; /* 0xf5 - rsvd */ -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 39d67c52d5..db84914070 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <compiler.h> #include <commonlib/helpers.h> #include <delay.h> #include <arch/io.h> @@ -73,7 +74,7 @@ typedef struct ich7_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; +} __packed ich7_spi_regs; typedef struct ich9_spi_regs { uint32_t bfpr; // 0 @@ -106,7 +107,7 @@ typedef struct ich9_spi_regs { uint32_t srdl; uint32_t srdc; uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; +} __packed ich9_spi_regs; typedef struct ich10_spi_regs { uint32_t bfpr; @@ -138,7 +139,7 @@ typedef struct ich10_spi_regs { uint32_t scs; uint32_t bcr; uint32_t tcgc; -} __attribute__((packed)) ich10_spi_regs; +} __packed ich10_spi_regs; typedef struct ich_spi_controller { int locked; diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 9db504f840..bdc6b45a56 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -130,4 +132,4 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 49c6fc1db5..c3a3920596 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -130,6 +132,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 49c6fc1db5..c3a3920596 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -130,6 +132,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 06495c1963..d62b22ad5e 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -98,7 +100,7 @@ struct me_did { u32 reserved: 8; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_GMES 0x48 #define ME_GMES_PHASE_ROM 0 @@ -124,7 +126,7 @@ struct me_gmes { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -136,7 +138,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -157,7 +159,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -175,7 +177,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -199,7 +201,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -210,7 +212,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 @@ -225,7 +227,7 @@ struct me_fw_version { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -255,7 +257,7 @@ typedef struct { u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u8 num_icc_profiles; @@ -263,7 +265,7 @@ typedef struct { u8 icc_profile_index; u8 reserved; u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u32 full_net : 1; @@ -286,7 +288,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; +} __packed mefwcaps_sku; typedef struct { u16 lock_state : 1; @@ -297,13 +299,13 @@ typedef struct { u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __packed tdt_state_info; typedef struct { u32 platform_target_usage_type : 4; @@ -313,7 +315,7 @@ typedef struct { u32 intel_me_fw_image_type : 4; u32 platform_brand : 4; u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; +} __packed platform_type_rule_data; typedef struct { mefwcaps_sku fw_capabilities; @@ -324,7 +326,7 @@ typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -350,20 +352,20 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; struct me_fwcaps { u32 id; u8 length; mefwcaps_sku caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 1c0011a823..6cd8ec3c4f 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -148,7 +149,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 64e9c31931..6c21db228e 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -16,6 +16,8 @@ #ifndef INTEL_LYNXPOINT_LP_GPIO_H #define INTEL_LYNXPOINT_LP_GPIO_H +#include <compiler.h> + /* LynxPoint LP GPIOBASE Registers */ #define GPIO_OWNER(set) (0x00 + ((set) * 4)) #define GPIO_PIRQ_APIC_EN 0x10 @@ -158,7 +160,7 @@ struct pch_lp_gpio_map { u8 reset; u8 blink; u8 pirq; -} __attribute__ ((packed)); +} __packed; /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 912fb62e37..a1987eb55e 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <compiler.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ @@ -75,7 +77,7 @@ struct me_hfs { u32 boot_options_present: 1; u32 ack_data: 3; u32 bios_msg_ack: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_UMA 0x44 @@ -85,7 +87,7 @@ struct me_uma { u32 valid: 1; u32 reserved_0: 14; u32 set_to_one: 1; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -100,7 +102,7 @@ struct me_did { u32 rapid_start: 1; u32 status: 4; u32 init_done: 4; -} __attribute__ ((packed)); +} __packed; /* * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according @@ -191,7 +193,7 @@ struct me_hfs2 { u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; -} __attribute__ ((packed)); +} __packed; #define PCI_ME_H_GS2 0x70 #define PCI_ME_MBP_GIVE_UP 0x01 @@ -206,7 +208,7 @@ struct me_heres { u32 reserved: 26; u32 extend_feature_present: 1; u32 extend_reg_valid: 1; -} __attribute__ ((packed)); +} __packed; /* * Management Engine MEI registers @@ -227,7 +229,7 @@ struct mei_csr { u32 buffer_read_ptr: 8; u32 buffer_write_ptr: 8; u32 buffer_depth: 8; -} __attribute__ ((packed)); +} __packed; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -245,7 +247,7 @@ struct mei_header { u32 length: 9; u32 reserved: 6; u32 is_complete: 1; -} __attribute__ ((packed)); +} __packed; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -268,7 +270,7 @@ struct mkhi_header { u32 is_response: 1; u32 reserved: 8; u32 result: 8; -} __attribute__ ((packed)); +} __packed; struct me_fw_version { u16 code_minor; @@ -279,7 +281,7 @@ struct me_fw_version { u16 recovery_major; u16 recovery_build_number; u16 recovery_hot_fix; -} __attribute__ ((packed)); +} __packed; /* ICC Messages */ #define ICC_SET_CLOCK_ENABLES 0x3 @@ -291,14 +293,14 @@ struct icc_header { u32 icc_status; u32 length; u32 reserved; -} __attribute__ ((packed)); +} __packed; struct icc_clock_enables_msg { u32 clock_enables; u32 clock_mask; u32 no_response: 1; u32 reserved: 31; -} __attribute__ ((packed)); +} __packed; #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 @@ -312,7 +314,7 @@ struct icc_clock_enables_msg { struct me_global_reset { u8 request_origin; u8 reset_type; -} __attribute__ ((packed)); +} __packed; typedef enum { ME_NORMAL_BIOS_PATH, @@ -373,21 +375,21 @@ typedef struct { u32 mbp_size : 8; u32 num_entries : 8; u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +} __packed mbp_header; typedef struct { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; +} __packed mbp_item_header; typedef struct { u32 major_version : 16; u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __attribute__ ((packed)) mbp_fw_version_name; +} __packed mbp_fw_version_name; typedef struct { u32 full_net : 1; @@ -409,13 +411,13 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mbp_mefwcaps; +} __packed mbp_mefwcaps; typedef struct { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __attribute__ ((packed)) mbp_rom_bist_data; +} __packed mbp_rom_bist_data; typedef struct { u32 key[8]; @@ -433,7 +435,7 @@ typedef struct { u32 image_type: 4; u32 brand: 4; u32 rsvd1: 16; -} __attribute__ ((packed)) mbp_me_firmware_type; +} __packed mbp_me_firmware_type; typedef struct { mbp_me_firmware_type rule_data; @@ -443,7 +445,7 @@ typedef struct { typedef struct { u16 icc_start_address; u16 mask; -} __attribute__ ((packed)) icc_address_mask; +} __packed icc_address_mask; typedef struct { u8 num_icc_profiles; @@ -452,7 +454,7 @@ typedef struct { u8 reserved; u32 icc_reg_bundles; icc_address_mask icc_address_mask[0]; -} __attribute__ ((packed)) mbp_icc_profile; +} __packed mbp_icc_profile; typedef struct { u16 lock_state : 1; @@ -461,24 +463,24 @@ typedef struct { u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; -} __attribute__ ((packed)) tdt_state_flag; +} __packed tdt_state_flag; typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) mbp_at_state; +} __packed mbp_at_state; typedef struct { u32 wake_event_mrst_time_ms; u32 mrst_pltrst_time_ms; u32 pltrst_cpurst_time_ms; -} __attribute__ ((packed)) mbp_plat_time; +} __packed mbp_plat_time; typedef struct { u32 device_type : 2; u32 reserved : 30; -} __attribute__ ((packed)) mbp_nfc_data; +} __packed mbp_nfc_data; typedef struct { mbp_fw_version_name *fw_version_name; @@ -498,6 +500,6 @@ struct me_fwcaps { u8 length; mbp_mefwcaps caps_sku; u8 reserved[3]; -} __attribute__ ((packed)); +} __packed; #endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 50936cf5e1..667a6dba1b 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <compiler.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -124,7 +125,7 @@ typedef struct { /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 7ab5faf961..0639fd1193 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -17,6 +17,7 @@ /* rl5c476 routines and defines*/ +#include <compiler.h> #include <stdint.h> @@ -87,4 +88,4 @@ typedef struct pc16reg { u8 resv8; u8 resv9; u8 smpga0; -} __attribute__ ((packed)) pc16reg_t; +} __packed pc16reg_t; diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h index 9e543d4222..894bfe89fa 100644 --- a/src/southbridge/via/vt8237r/nvs.h +++ b/src/southbridge/via/vt8237r/nvs.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <compiler.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -38,4 +40,4 @@ typedef struct { u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ -} __attribute__((packed)) global_nvs_t; +} __packed global_nvs_t; diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 95f9750a40..e195a299d9 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H #define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H +#include <compiler.h> + /* Static resources for the VT8237R southbridge */ #define VT8237R_APIC_ID 0x2 @@ -121,7 +123,7 @@ struct vt8237_network_rom { u8 cfg_c; u8 cfg_d; u8 checksum; -} __attribute__ ((packed)); +} __packed; #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 |