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-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig1
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc2
-rw-r--r--src/southbridge/intel/lynxpoint/early_smbus.c34
3 files changed, 2 insertions, 35 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 2207028ee8..3071fae62b 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -9,6 +9,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 48be615509..16daa10e88 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -33,7 +33,7 @@ smm-y += smihandler.c me_9.x.c pch.c
smm-y += pmutil.c usb_ehci.c usb_xhci.c
bootblock-y += early_pch.c
-romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
+romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
deleted file mode 100644
index 85f20a745c..0000000000
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <device/smbus_host.h>
-#include "pch.h"
-
-uintptr_t smbus_base(void)
-{
- return CONFIG_FIXED_SMBUS_IO_BASE;
-}
-
-int smbus_enable_iobar(uintptr_t base)
-{
- /* Set the SMBus device statically. */
- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
- /* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
- return -1;
-
- /* Set SMBus I/O base. */
- pci_write_config32(dev, SMB_BASE,
- base | PCI_BASE_ADDRESS_SPACE_IO);
-
- /* Set SMBus enable. */
- pci_write_config8(dev, HOSTC, HST_EN);
-
- /* Set SMBus I/O space enable. */
- pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-
- return 0;
-}