10 files changed, 211 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index b346863d07..af305eed72 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON
 	bool
 	select IOAPIC
 	select HAVE_USBDEBUG
+	select HAVE_HARD_RESET
 
 if SOUTHBRIDGE_AMD_AGESA_HUDSON
 
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
index e98d3ed22d..97cdf1c229 100644
--- a/src/southbridge/amd/cimx/sb700/Kconfig
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700
 	bool
 	select IOAPIC
 	select AMD_SB_CIMX
+	select HAVE_HARD_RESET
 
 if SOUTHBRIDGE_AMD_CIMX_SB700
 config SATA_CONTROLLER_MODE
diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc
index 94a0deadd6..268629f45c 100644
--- a/src/southbridge/amd/cimx/sb700/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb700/Makefile.inc
@@ -22,8 +22,10 @@
 
 romstage-y += early.c
 romstage-y += smbus.c
+romstage-y += reset.c
 
 ramstage-y += late.c
+ramstage-y += reset.c
 
 ramstage-y   += smbus.c
 ramstage-y   += lpc.c
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
new file mode 100644
index 0000000000..7a96aa4595
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
+#include <reset.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 554d8c7009..b82409d883 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
 	default n
 	select IOAPIC
 	select AMD_SB_CIMX
+	select HAVE_HARD_RESET
 
 if SOUTHBRIDGE_AMD_CIMX_SB800
 config BOOTBLOCK_SOUTHBRIDGE_INIT
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 524c2d3274..831cc2ecbd 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -23,9 +23,11 @@
 romstage-y += cfg.c
 romstage-y += early.c
 romstage-y += smbus.c
+romstage-y += reset.c
 
 ramstage-y += cfg.c
 ramstage-y += late.c
+ramstage-y += reset.c
 
 ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c
 ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
new file mode 100644
index 0000000000..7a96aa4595
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
+#include <reset.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index aa30e561c6..5d3b0a1328 100755
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB900
 	default n
 	select IOAPIC
 	select AMD_SB_CIMX
+	select HAVE_HARD_RESET
 
 if SOUTHBRIDGE_AMD_CIMX_SB900
 config SATA_CONTROLLER_MODE
diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc
index ebb3e3f62d..cc4c553590 100755
--- a/src/southbridge/amd/cimx/sb900/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb900/Makefile.inc
@@ -23,10 +23,12 @@
 romstage-y += cfg.c
 romstage-y += early.c
 romstage-y += smbus.c
+romstage-y += reset.c
 
 ramstage-y += cfg.c
 ramstage-y += early.c
 ramstage-y += late.c
+ramstage-y += reset.c
 
 ramstage-y   += smbus.c
 ramstage-y   += lpc.c
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
new file mode 100644
index 0000000000..7a96aa4595
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
+#include <reset.h>
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+