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-rw-r--r--src/southbridge/intel/bd82x6x/pch.h4
-rw-r--r--src/southbridge/intel/bd82x6x/pci.c9
-rw-r--r--src/southbridge/intel/bd82x6x/pcie.c10
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h4
-rw-r--r--src/southbridge/intel/i82801gx/pci.c9
-rw-r--r--src/southbridge/intel/i82801gx/pcie.c10
-rw-r--r--src/southbridge/intel/i82801ix/pcie.c9
-rw-r--r--src/southbridge/intel/i82801jx/pcie.c9
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h4
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c10
11 files changed, 35 insertions, 47 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index cb0691fea2..22b91073ce 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -101,10 +101,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index a222893d88..833512a5b7 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "pch.h"
@@ -36,10 +37,10 @@ static void pci_init(struct device *dev)
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 &= ~PCI_BRIDGE_CTL_SERR;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 686930d80a..739f6ce8a8 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -232,11 +233,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 7fc0114aac..d615b403ac 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -59,10 +59,6 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
#define ICH_PCIE_DEV_SLOT 28
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 4d98e8939a..d493b790a7 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
@@ -35,10 +36,10 @@ static void pci_init(struct device *dev)
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 &= ~PCI_BRIDGE_CTL_SERR;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 0946a9aadf..0d8b474d9b 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "chip.h"
@@ -67,11 +68,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 3b90ce6471..b1d0ecc214 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -41,10 +42,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index 84b2b6a3fa..64da5a734b 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -41,10 +42,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index e7cc9d2c7c..f7b29291db 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -82,10 +82,6 @@ void pch_enable(struct device *dev);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3f37887567..be4285b1da 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -195,10 +195,6 @@ void mainboard_config_superio(void);
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
/* Power Management Control and Status */
#define PCH_PCS 0x84
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index a3b2e096d8..1eb8e4bcc4 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@@ -684,11 +685,10 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 14:40:38 +0000