summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/common/Makefile.inc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 3224e1fcf1..3ad79248a0 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -22,6 +22,9 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
+
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
romstage-y += pmbase.c
@@ -37,9 +40,6 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
-romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
-ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
-
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c