summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5535/early_setup.c6
-rw-r--r--src/southbridge/amd/cs5536/early_setup.c2
2 files changed, 2 insertions, 6 deletions
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 1a612cc55f..4a2e1b4965 100644
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
@@ -107,15 +107,11 @@ static void cs5535_setup_cis_mode(void)
{
msr_t msr;
- /* setup CPU interface serial to mode C on both sides */
+ /* Setup CPU serial SouthBridge interface to mode C. */
msr = rdmsr(GLPCI_SB_CTRL);
msr.lo &= ~0x18;
msr.lo |= 0x10;
wrmsr(GLPCI_SB_CTRL, msr);
- //Only do this if we are building for 5535
- msr.lo = 0x2;
- msr.hi = 0x0;
- wrmsr(VIP_GIO_MSR_SEL, msr);
}
static void dummy(void)
diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
index 0a35964ef2..7d982433d4 100644
--- a/src/southbridge/amd/cs5536/early_setup.c
+++ b/src/southbridge/amd/cs5536/early_setup.c
@@ -145,7 +145,7 @@ static void cs5536_setup_cis_mode(void)
{
msr_t msr;
- /* setup CPU interface serial to mode B to match CPU */
+ /* Setup CPU serial SouthBridge interface to mode C. */
msr = rdmsr(GLPCI_SB_CTRL);
msr.lo &= ~0x18;
msr.lo |= 0x10;