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-rw-r--r--src/southbridge/intel/i3100/cmos_failover.c35
-rw-r--r--src/southbridge/intel/i82801ax/Makefile.inc2
-rw-r--r--src/southbridge/intel/i82801ax/cmos_failover.c32
-rw-r--r--src/southbridge/intel/i82801bx/Makefile.inc2
-rw-r--r--src/southbridge/intel/i82801bx/cmos_failover.c32
-rw-r--r--src/southbridge/intel/i82801cx/cmos_failover.c19
-rw-r--r--src/southbridge/intel/i82801dx/cmos_failover.c35
-rw-r--r--src/southbridge/intel/i82801ex/cmos_failover.c16
-rw-r--r--src/southbridge/intel/i82801gx/cmos_failover.c36
-rw-r--r--src/southbridge/ti/pci7420/pci7420_cardbus.c4
-rw-r--r--src/southbridge/ti/pci7420/pci7420_firewire.c2
11 files changed, 2 insertions, 213 deletions
diff --git a/src/southbridge/intel/i3100/cmos_failover.c b/src/southbridge/intel/i3100/cmos_failover.c
deleted file mode 100644
index 4a134dd609..0000000000
--- a/src/southbridge/intel/i3100/cmos_failover.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i3100.h"
-
-#define RTC_FAILED (1 <<2)
-#define GEN_PMCON_3 0xa4
-
-static void check_cmos_failed(void)
-{
- u8 byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- if (byte & RTC_FAILED) {
- // clear bit 1 and bit 2
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-}
diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc
index 3e66f04569..5544caeec6 100644
--- a/src/southbridge/intel/i82801ax/Makefile.inc
+++ b/src/southbridge/intel/i82801ax/Makefile.inc
@@ -32,7 +32,5 @@ driver-y += i82801ax_usb_ehci.o
obj-y += i82801ax_reset.o
obj-y += i82801ax_watchdog.o
-# TODO: What about cmos_failover.c?
-
# TODO: Fix and enable i82801ax_smbus.o later.
diff --git a/src/southbridge/intel/i82801ax/cmos_failover.c b/src/southbridge/intel/i82801ax/cmos_failover.c
deleted file mode 100644
index a770005b73..0000000000
--- a/src/southbridge/intel/i82801ax/cmos_failover.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i82801ax.h"
-
-static void check_cmos_failed(void)
-{
- uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- if (byte & RTC_FAILED) {
- //clear bit 1 and bit 2
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-}
diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc
index 3d7d61836a..cce5394af8 100644
--- a/src/southbridge/intel/i82801bx/Makefile.inc
+++ b/src/southbridge/intel/i82801bx/Makefile.inc
@@ -32,7 +32,5 @@ driver-y += i82801bx_usb_ehci.o
obj-y += i82801bx_reset.o
obj-y += i82801bx_watchdog.o
-# TODO: What about cmos_failover.c?
-
# TODO: Fix and enable i82801bx_smbus.o later.
diff --git a/src/southbridge/intel/i82801bx/cmos_failover.c b/src/southbridge/intel/i82801bx/cmos_failover.c
deleted file mode 100644
index d2e4081da0..0000000000
--- a/src/southbridge/intel/i82801bx/cmos_failover.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i82801bx.h"
-
-static void check_cmos_failed(void)
-{
- uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- if (byte & RTC_FAILED) {
- //clear bit 1 and bit 2
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-}
diff --git a/src/southbridge/intel/i82801cx/cmos_failover.c b/src/southbridge/intel/i82801cx/cmos_failover.c
deleted file mode 100644
index ab1816fbd8..0000000000
--- a/src/southbridge/intel/i82801cx/cmos_failover.c
+++ /dev/null
@@ -1,19 +0,0 @@
-//kind of cmos_err for ich3
-
-#include "i82801cx.h"
-
-static void check_cmos_failed(void)
-{
-#if CONFIG_HAVE_OPTION_TABLE
- uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
-
- if( byte & RTC_BATTERY_DEAD) {
- // Set boot_option and last_boot to 'Fallback',
- // clear reboot_bits
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-#endif
-}
diff --git a/src/southbridge/intel/i82801dx/cmos_failover.c b/src/southbridge/intel/i82801dx/cmos_failover.c
deleted file mode 100644
index 3654a0ae0c..0000000000
--- a/src/southbridge/intel/i82801dx/cmos_failover.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ron G. Minnich
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-// kind of cmos_err for ICH4
-#define RTC_FAILED (1 <<2)
-#define GEN_PMCON_3 0xa4
-static void check_cmos_failed(void)
-{
- u8 byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- if (byte & RTC_FAILED) {
- //clear bit 1 and bit 2
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-}
diff --git a/src/southbridge/intel/i82801ex/cmos_failover.c b/src/southbridge/intel/i82801ex/cmos_failover.c
deleted file mode 100644
index 4821fad3d2..0000000000
--- a/src/southbridge/intel/i82801ex/cmos_failover.c
+++ /dev/null
@@ -1,16 +0,0 @@
-//kind of cmos_err for ich5
-#define RTC_FAILED (1 <<2)
-#define GEN_PMCON_3 0xa4
-static void check_cmos_failed(void)
-{
-
- uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
- if( byte & RTC_FAILED){
-//clear bit 1 and bit 2
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-}
diff --git a/src/southbridge/intel/i82801gx/cmos_failover.c b/src/southbridge/intel/i82801gx/cmos_failover.c
deleted file mode 100644
index f26fd4ffd9..0000000000
--- a/src/southbridge/intel/i82801gx/cmos_failover.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i82801gx.h"
-
-#define RTC_FAILED (1 << 2)
-#define GEN_PMCON_3 0xa4
-
-static void check_cmos_failed(void)
-{
- u8 byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- if (byte & RTC_FAILED) {
- // clear bit 1 and bit 2
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0x0c;
- byte |= CONFIG_MAX_REBOOT_CNT << 4;
- cmos_write(byte, RTC_BOOT_BYTE);
- }
-}
diff --git a/src/southbridge/ti/pci7420/pci7420_cardbus.c b/src/southbridge/ti/pci7420/pci7420_cardbus.c
index 7165822ea7..4814d97707 100644
--- a/src/southbridge/ti/pci7420/pci7420_cardbus.c
+++ b/src/southbridge/ti/pci7420/pci7420_cardbus.c
@@ -83,12 +83,12 @@ static void pci7420_cardbus_init(device_t dev)
#endif
}
-void pci7420_cardbus_read_resources(device_t dev)
+static void pci7420_cardbus_read_resources(device_t dev)
{
cardbus_read_resources(dev);
}
-void pci7420_cardbus_set_resources(device_t dev)
+static void pci7420_cardbus_set_resources(device_t dev)
{
printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));
diff --git a/src/southbridge/ti/pci7420/pci7420_firewire.c b/src/southbridge/ti/pci7420/pci7420_firewire.c
index 4d855b30b5..bd09c2fde7 100644
--- a/src/southbridge/ti/pci7420/pci7420_firewire.c
+++ b/src/southbridge/ti/pci7420/pci7420_firewire.c
@@ -30,8 +30,6 @@
static void pci7420_firewire_init(device_t dev)
{
- u8 reg8;
-
printk(BIOS_DEBUG, "TI PCI7420/7620 FireWire init\n");
#ifdef ODD_IRQ_FIXUP
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 20:28:11 +0000