diff options
Diffstat (limited to 'src/southbridge')
35 files changed, 47 insertions, 47 deletions
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 20212ef223..1f60bc4ed9 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -70,14 +70,14 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); /* Initialize the real time clock. - * The 0 argument tells rtc_init not to + * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. - * 1 tells rtc_init to always initialize the CMOS. + * 1 tells cmos_init to always initialize the CMOS. */ - rtc_init(0); + cmos_init(0); } static void hudson_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 8cabcab842..718b40bf9d 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -77,7 +77,7 @@ static void lpc_init(struct device *dev) } /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* Initialize isa dma */ isa_dma_init(); diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 42330ca1e9..20da0733f0 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -80,14 +80,14 @@ static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); /* Initialize the real time clock. - * The 0 argument tells rtc_init not to + * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. - * 1 tells rtc_init to always initialize the CMOS. + * 1 tells cmos_init to always initialize the CMOS. */ - rtc_init(0); + cmos_init(0); setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b132bf17d0..7d6e221a6f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -132,14 +132,14 @@ static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); /* Initialize the real time clock. - * The 0 argument tells rtc_init not to + * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. - * 1 tells rtc_init to always initialize the CMOS. + * 1 tells cmos_init to always initialize the CMOS. */ - rtc_init(0); + cmos_init(0); setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */ diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 7303bdceba..8d9b486831 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -102,14 +102,14 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); /* Initialize the real time clock. - * The 0 argument tells rtc_init not to + * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. - * 1 tells rtc_init to always initialize the CMOS. + * 1 tells cmos_init to always initialize the CMOS. */ - rtc_init(0); + cmos_init(0); setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index e305594b7f..1f7eab87ad 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -245,7 +245,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb) msr.lo = RTC_MONA; wrmsr(MDD_RTC_MONA_IND, msr); - rtc_init(0); + cmos_init(0); isa_dma_init(); } diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7f1ca2597a..d8e63b557c 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 8de39a6429..a8e72c28f7 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -169,7 +169,7 @@ static void sm_init(device_t dev) /* ab index */ pci_write_config32(dev, 0xF0, AB_INDX); /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */ abcfg_reg(0x10060, 9 << 17, 9 << 17); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 6995861a8d..173de8369f 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -90,7 +90,7 @@ static void lpc_init(device_t dev) } #endif - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); } void backup_top_of_ram(uint64_t ramtop) diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 0fb6556f37..8bb5378ff7 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -197,7 +197,7 @@ static void sm_init(device_t dev) /* ab index */ pci_write_config32(dev, 0xF0, AB_INDX); /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* 4.3 Enabling Upstream DMA Access */ axcfg_reg(0x04, 1 << 2, 1 << 2); diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 12fd96fbfa..7a4dd831da 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -67,7 +67,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(RTC_HAS_ALTCENTURY); } static void sb800_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 315bc20b72..acdfb090a6 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -111,7 +111,7 @@ static void sm_init(device_t dev) pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF); pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF); /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); byte = pm_ioread(0x8); byte |= 1 << 2 | 1 << 4; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 834f0a1a4b..af79892a7b 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -33,7 +33,7 @@ static void lpc_init(device_t dev) { /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* Initialize isa dma */ isa_dma_init(); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index a2b1246c71..d4f263bab1 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -595,7 +595,7 @@ static void southbridge_init(struct device *dev) pci_routing_fixup(dev); fix_cmos_rtc_time(); - rtc_init(0); + cmos_init(0); /* Check keyboard controller ready. If timeout, reload firmware code * and try again. */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 75b8a6c91e..0e3a4f6466 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev) } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } /* CougarPoint PCH Power Management init */ diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index 67bcadc961..b5b77efa14 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -297,7 +297,7 @@ static void lpc_init(struct device *dev) esb6300_gpio_init(dev); /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* Initialize isa dma */ isa_dma_init(); diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 2fc3ea7e7b..e5d63b66db 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -305,7 +305,7 @@ static void pch_rtc_init(struct device *dev) } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } /* CougarPoint PCH Power Management init */ diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 0697785b21..bd3d12ccb5 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -69,7 +69,7 @@ static void reset_rtc(void) write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS); } - rtc_init(rtc_failed); + cmos_init(rtc_failed); } void rangeley_sb_early_initialization(void) diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 7c79e5879d..ba74f30748 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -375,7 +375,7 @@ static void lpc_init(struct device *dev) i3100_gpio_init(dev); /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* Initialize isa dma */ isa_dma_init(); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 5605106ddf..5261fbafa3 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -64,7 +64,7 @@ static void isa_init(struct device *dev) u32 reg32; /* Initialize the real time clock (RTC). */ - rtc_init(0); + cmos_init(0); /* * Enable special cycles, needed for soft poweroff. diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 212c95f270..11519c1fb3 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -190,7 +190,7 @@ static void i82801ax_rtc_init(struct device *dev) } reg32 = pci_read_config32(dev, GEN_STA); rtc_failed |= reg32 & (1 << 2); - rtc_init(rtc_failed); + cmos_init(rtc_failed); /* Enable access to the upper 128 byte bank of CMOS RAM. */ pci_write_config8(dev, RTC_CONF, 0x04); diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 13b15996dc..278d65c3c1 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -205,7 +205,7 @@ static void i82801bx_rtc_init(struct device *dev) } reg32 = pci_read_config32(dev, GEN_STS); rtc_failed |= reg32 & (1 << 2); - rtc_init(rtc_failed); + cmos_init(rtc_failed); /* Enable access to the upper 128 byte bank of CMOS RAM. */ pci_write_config8(dev, RTC_CONF, 0x04); diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f9c0ece4fe..f6c33b7feb 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -108,7 +108,7 @@ static void i82801cx_rtc_init(struct device *dev) dword = pci_read_config32(dev, GEN_STS); rtc_failed |= dword & (1 << 2); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index de09b165d6..1b23fad832 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -200,7 +200,7 @@ static void i82801dx_rtc_init(struct device *dev) } reg32 = pci_read_config32(dev, GEN_STS); rtc_failed |= reg32 & (1 << 2); - rtc_init(rtc_failed); + cmos_init(rtc_failed); /* Enable access to the upper 128 byte bank of CMOS RAM. */ pci_write_config8(dev, RTC_CONF, 0x04); diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index fb1586eb12..1823e65cf4 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -308,7 +308,7 @@ static void lpc_init(struct device *dev) i82801ex_gpio_init(dev); /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* Initialize isa dma */ isa_dma_init(); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 80abb78861..10e40be608 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -294,7 +294,7 @@ static void i82801gx_rtc_init(struct device *dev) } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } static void enable_hpet(void) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 8105a4dc16..664088cd22 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -326,7 +326,7 @@ static void i82801ix_rtc_init(struct device *dev) } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } static void enable_hpet(void) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 31bb4e7921..a833a3d83a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev) } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } static void mobile5_pm_init(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 64b835f870..a2024242c2 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -301,7 +301,7 @@ static void pch_rtc_init(struct device *dev) } printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - rtc_init(rtc_failed); + cmos_init(rtc_failed); } /* LynxPoint PCH Power Management init */ diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b68785ab76..9b6049c993 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -162,7 +162,7 @@ static void lpc_init(device_t dev) outb(byte, 0x70); /* Initialize the real time clock (RTC). */ - rtc_init(0); + cmos_init(0); /* Initialize ISA DMA. */ isa_dma_init(); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index ef3c6f655e..11c2c4f612 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -152,7 +152,7 @@ static void lpc_init(device_t dev) outb(byte, 0x70); /* Initialize the real time clock. */ - rtc_init(0); + cmos_init(0); /* Initialize ISA DMA. */ isa_dma_init(); diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 824bb6a174..0e11c6f9b7 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -148,7 +148,7 @@ static void lpc_init(device_t dev) } /* Initialize the real time clock */ - rtc_init(0); + cmos_init(0); /* Initialize isa dma */ isa_dma_init(); diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c index 40854dbcf7..c6b74fdaa1 100644 --- a/src/southbridge/via/vt8231/lpc.c +++ b/src/southbridge/via/vt8231/lpc.c @@ -121,7 +121,7 @@ static void vt8231_init(struct device *dev) //ethernet_fixup(); // Start the rtc - rtc_init(0); + cmos_init(0); } static void vt8231_read_resources(device_t dev) diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c index b355ad0d88..2c7848179a 100644 --- a/src/southbridge/via/vt8235/lpc.c +++ b/src/southbridge/via/vt8235/lpc.c @@ -209,7 +209,7 @@ static void vt8235_init(struct device *dev) pci_write_config8(dev, 0x40, 0x54); // Start the rtc - rtc_init(0); + cmos_init(0); } /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 5ddd816153..9e8f6f62e5 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -565,7 +565,7 @@ static void vt8237_common_init(struct device *dev) setup_pm(dev); /* Start the RTC. */ - rtc_init(0); + cmos_init(0); } static void vt8237r_read_resources(device_t dev) |