diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/ti/pci1x2x/chip.h | 3 | ||||
| -rw-r--r-- | src/southbridge/ti/pci1x2x/pci1x2x.c | 6 |
2 files changed, 0 insertions, 9 deletions
diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h index b40194e328..4c3676153d 100644 --- a/src/southbridge/ti/pci1x2x/chip.h +++ b/src/southbridge/ti/pci1x2x/chip.h @@ -6,8 +6,5 @@ extern struct chip_operations southbridge_ti_pci1x2x_ops; struct southbridge_ti_pci1x2x_config { int scr; int mrr; - int clsr; - int cltr; - int bcr; }; #endif diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index dfb183cd27..e59be4fd2c 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -34,12 +34,6 @@ static void ti_pci1x2y_init(struct device *dev) struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; if (conf) { - /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, conf->clsr); - /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, conf->cltr); - /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, conf->bcr); /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ |