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-rw-r--r--src/southbridge/amd/agesa/hudson/enable_usbdebug.c1
-rw-r--r--src/southbridge/amd/sb600/Kconfig4
-rw-r--r--src/southbridge/amd/sb600/enable_usbdebug.c3
-rw-r--r--src/southbridge/amd/sb700/enable_usbdebug.c5
-rw-r--r--src/southbridge/amd/sb800/enable_usbdebug.c1
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig4
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig4
-rw-r--r--src/southbridge/nvidia/ck804/enable_usbdebug.c3
-rw-r--r--src/southbridge/nvidia/mcp55/enable_usbdebug.c3
-rw-r--r--src/southbridge/sis/sis966/enable_usbdebug.c3
10 files changed, 0 insertions, 31 deletions
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index dda29c1724..6fa17817f9 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -57,5 +57,4 @@ void enable_usbdebug(unsigned int port)
EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2),
PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- set_debug_port(port);
}
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index 4ae4641b86..fe9468d4af 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET
hex
default 0xe0
-config USBDEBUG_DEFAULT_PORT
- int
- default 0
-
choice
prompt "SATA Mode"
default SATA_MODE_IDE
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index d20c8c4fe1..40c53aecfa 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -36,9 +36,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
- /* Select the requested physical USB port (1-15) as the Debug Port. */
- set_debug_port(port);
-
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 3aaf7c82bf..0712d2af2d 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -58,9 +58,4 @@ void enable_usbdebug(unsigned int port)
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
- /*
- * Select the requested physical USB port (1-15) as the Debug Port.
- * Must be called after the EHCI BAR has been set up (see above).
- */
- set_debug_port(port);
}
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 09f742915d..6422fa2295 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -57,5 +57,4 @@ void enable_usbdebug(unsigned int port)
EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2),
PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- set_debug_port(port);
}
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index d4a6baa2ce..62c6b436f2 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET
hex
default 0xa0
-config USBDEBUG_DEFAULT_PORT
- int
- default 1
-
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801gx/bootblock.c"
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index dd07dac7a2..8a4a53ef78 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -37,10 +37,6 @@ config EHCI_DEBUG_OFFSET
hex
default 0xa0
-config USBDEBUG_DEFAULT_PORT
- int
- default 1
-
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801ix/bootblock.c"
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 90890e6802..d65fea212d 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -52,9 +52,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
- /* Mark the requested physical USB port (1-15) as the Debug Port. */
- set_debug_port(port);
-
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 069344b522..f629c505c3 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -46,9 +46,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
- /* Mark the requested physical USB port (1-15) as the Debug Port. */
- set_debug_port(port);
-
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index f38fe90398..04384ba9ac 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -48,9 +48,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
- /* Mark the requested physical USB port (1-15) as the Debug Port. */
- set_debug_port(port);
-
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);