diff options
Diffstat (limited to 'src/southbridge/via')
| -rw-r--r-- | src/southbridge/via/k8t890/Config.lb | 25 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890.h | 35 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_ctrl.c | 102 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_dram.c | 78 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_early_car.c | 56 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_host.c | 45 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_host_ctrl.c | 93 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_pcie.c | 164 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_traf_ctrl.c | 121 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/romstrap.inc | 61 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/romstrap.lds | 29 |
11 files changed, 809 insertions, 0 deletions
diff --git a/src/southbridge/via/k8t890/Config.lb b/src/southbridge/via/k8t890/Config.lb new file mode 100644 index 0000000000..e18c1a20bc --- /dev/null +++ b/src/southbridge/via/k8t890/Config.lb @@ -0,0 +1,25 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License v2 as published by +## the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver k8t890_ctrl.o +driver k8t890_dram.o +driver k8t890_host.o +driver k8t890_host_ctrl.o +driver k8t890_pcie.o +driver k8t890_traf_ctrl.o diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h new file mode 100644 index 0000000000..d719af6082 --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890.h @@ -0,0 +1,35 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_VIA_K8T890_K8T890_H +#define SOUTHBRIDGE_VIA_K8T890_K8T890_H + +/* Static resources for K8T890. */ +#define K8T890_APIC_ID 0x3 + +/* + * Please check the datasheet and traf_ctrl_enable before change! + * It can't be changed to an arbitrary address. + */ +#define K8T890_APIC_BASE 0xfecc0000 + +#define K8T890_MMCONFIG_MBAR 0x61 +#define K8T890_MULTIPLE_FN_EN 0x4f + +#endif diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c new file mode 100644 index 0000000000..d45cd59998 --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_ctrl.c @@ -0,0 +1,102 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +static void ctrl_enable(struct device *dev) +{ + u8 regm, regm2, regm3; + device_t devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + + /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] + should to 1 */ + + /* C2P Read ACK Return Priority */ + /* PCI CFG Address bits[27:24] are used as extended register address + bit[11:8] */ + pci_write_config8(dev, 0x47, 0x30); + + /* FIXME: Program V-link 8X 16bit full duplex, this needs to be fixed + for other than VT8237R SB */ + pci_write_config8(dev, 0x48, 0x23); + + /* Magic init. This is not well documented :/ */ + pci_write_config8(dev, 0x70, 0xc2); + + /* PCI Control */ + pci_write_config8(dev, 0x72, 0xee); + pci_write_config8(dev, 0x73, 0x01); + pci_write_config8(dev, 0x74, 0x24); + pci_write_config8(dev, 0x75, 0x0f); + pci_write_config8(dev, 0x76, 0x50); + pci_write_config8(dev, 0x77, 0x08); + pci_write_config8(dev, 0x78, 0x01); + /* APIC on HT */ + pci_write_config8(dev, 0x7c, 0x7f); + pci_write_config8(dev, 0x7f, 0x02); + + /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ + + regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x57, regm); + + regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ + pci_write_config8(dev, 0x61, regm); + + regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ + pci_write_config8(dev, 0x62, regm); + + regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ + pci_write_config8(dev, 0xe6, regm); + + regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + + /* + * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! + * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00, + * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64! + */ + if (regm3 == 0xff) + regm3 = 0xc0; + else + regm3 = 0x0; + + /* Shadow page F + memhole copy */ + regm = pci_read_config8(devfun3, 0x83); + pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); +} + +static struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_7, +}; diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c new file mode 100644 index 0000000000..27134249dc --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_dram.c @@ -0,0 +1,78 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +static void dram_enable(struct device *dev) +{ + msr_t msr; + u16 reg; + + /* + * Enable Lowest Interrupt arbitration for APIC, enable NB APIC + * decoding, MSI support, no SMRAM, compatible SMM. + */ + pci_write_config8(dev, 0x86, 0x39); + + /* + * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if + * memory is doing K8 the DMA from SB will fail if we have it wrong, + * AND even we have it here, we must later copy it to SB to make it work :/ + */ + + /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for + * C0000-C3FFF etc. + */ + pci_write_config8(dev, 0x80, 0xff); + /* For page D0000-DFFFF */ + pci_write_config8(dev, 0x81, 0xff); + /* For page E0000-EFFFF */ + pci_write_config8(dev, 0x82, 0xff); + pci_write_config8(dev, 0x83, 0x30); + + msr = rdmsr(TOP_MEM); + reg = pci_read_config16(dev, 0x84); + reg &= 0xf; + pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + + reg = pci_read_config16(dev, 0x88); + reg &= 0xf800; + + pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); +} + +static struct device_operations dram_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = dram_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &dram_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_3, +}; diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c new file mode 100644 index 0000000000..d66801e7e5 --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_early_car.c @@ -0,0 +1,56 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Seems the link and width of HT link needs to be setup too, you need to + * generate PCI reset or LDTSTOP to apply. + */ + +u8 k8t890_early_setup_car(u8 width, u8 speed) +{ + u8 awidth, aspeed; + + print_debug("LDT width and speed for K8T890 was"); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + print_debug_hex8(awidth); + + aspeed = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); + print_debug_hex8(aspeed); + + if ((aspeed == speed) && (((width == 16) && (awidth == 0x11)) || + ((width == 8) && (awidth == 0x00)))) + return 0; + + /* Update the desired HT LNK capabilities in NB too. */ + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, + (width == 16) ? 0x11 : 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, speed); + + print_debug(" and will after HT reset: "); + + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + print_debug_hex8(awidth); + + aspeed = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); + print_debug_hex8(aspeed); + + print_debug("\n"); + + return 1; +} diff --git a/src/southbridge/via/k8t890/k8t890_host.c b/src/southbridge/via/k8t890/k8t890_host.c new file mode 100644 index 0000000000..ee2a374828 --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_host.c @@ -0,0 +1,45 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include "k8t890.h" + +static void host_enable(struct device *dev) +{ + /* Multiple function control */ + pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); +} + +static struct device_operations host_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &host_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_0, +}; diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c new file mode 100644 index 0000000000..05e981975c --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c @@ -0,0 +1,93 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +/* This fine tunes the HT link settings, which were loaded by ROM strap. */ +static void host_ctrl_enable(struct device *dev) +{ + dump_south(dev); + + /* + * Bit 4 is reserved but set by AW. Set PCI to HT outstanding + * requests to 3. + */ + pci_write_config8(dev, 0xa0, 0x13); + + /* Disable NVRAM and enable non-posted PCI writes. */ + pci_write_config8(dev, 0xa1, 0x8e); + + /* + * NVRAM I/O base 0xe00-0xeff, but it is disabled. + * Some bits are set and reserved. + */ + pci_write_config8(dev, 0xa2, 0x0e); + /* Arbitration control, some bits are reserved. */ + pci_write_config8(dev, 0xa5, 0x3c); + + /* Arbitration control 2 */ + pci_write_config8(dev, 0xa6, 0x80); + + writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */ + writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */ + writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */ + writeback(dev, 0xa3, 0x31); + writeback(dev, 0xa4, 0x30); + + writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */ + writeback(dev, 0xa6, 0x80); /* Some bits reserved. */ + writeback(dev, 0xa7, 0x86); /* Some bits reserved. */ + writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */ + writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */ + writeback(dev, 0xaa, 0x44); + writeback(dev, 0xab, 0x22); + writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */ + + writeback(dev, 0xae, 0x22); + writeback(dev, 0xaf, 0x40); + /* b0 is missing. */ + writeback(dev, 0xb1, 0x13); + writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */ + writeback(dev, 0xc0, 0x20); + writeback(dev, 0xc1, 0xaa); + writeback(dev, 0xc2, 0xaa); + writeback(dev, 0xc3, 0x02); + writeback(dev, 0xc4, 0x50); + writeback(dev, 0xc5, 0x50); + + dump_south(dev); +} + +static struct device_operations host_ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &host_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_2, +}; diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/k8t890_pcie.c new file mode 100644 index 0000000000..dec2348aac --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_pcie.c @@ -0,0 +1,164 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> + +void peg_init(struct device *dev) +{ + u8 reg; + + printk_debug("Configuring PCIe PEG\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + + /* Award has 0xb, VIA recomends 0x4. */ + pci_write_config8(dev, 0xe1, 0xb); + + /* + * pci_write_config8(dev, 0xe2, 0x0); + * pci_write_config8(dev, 0xe3, 0x92); + */ + /* Disable scrambling bit 6 to 1. */ + pci_write_config8(dev, 0xc0, 0x43); + + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */ + reg = pci_read_config8(dev, 0xb8); + pci_write_config8(dev, 0xb8, reg | 0x1); + + /* + * Downstream wait and Upstream Checking Malformed TLP through + * "Byte Enable Rule" And "Over 4K Boundary Rule". + */ + reg = pci_read_config8(dev, 0xa4); + pci_write_config8(dev, 0xa4, reg | 0x30); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Retrain link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x20); + + reg = pci_read_config8(dev, 0x3e); + reg |= 0x40; /* Bus reset. */ + pci_write_config8(dev, 0x3e, reg); + + reg = pci_read_config8(dev, 0x3e); + reg &= ~0x40; /* Clear reset. */ + pci_write_config8(dev, 0x3e, reg); + + dump_south(dev); +} + +void pcie_init(struct device *dev) +{ + u8 reg; + + printk_debug("Configuring PCIe PEXs\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + + /* Award has 0xb, VIA recommends 0x4. */ + pci_write_config8(dev, 0xe1, 0xb); + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Retrain. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x20); + + reg = pci_read_config8(dev, 0x3e); + reg |= 0x40; /* Bus reset. */ + pci_write_config8(dev, 0x3e, reg); + + reg = pci_read_config8(dev, 0x3e); + reg &= ~0x40; /* Clear reset. */ + pci_write_config8(dev, 0x3e, reg); + + dump_south(dev); +} + +static struct device_operations peg_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = peg_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &peg_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG, +}; + +static struct pci_driver pcie_drvd3f0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0, +}; + +static struct pci_driver pcie_drvd3f1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1, +}; + +static struct pci_driver pcie_drvd3f2 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2, +}; + +static struct pci_driver pcie_drvd3f3 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3, +}; diff --git a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c b/src/southbridge/via/k8t890/k8t890_traf_ctrl.c new file mode 100644 index 0000000000..6e6f8c86aa --- /dev/null +++ b/src/southbridge/via/k8t890/k8t890_traf_ctrl.c @@ -0,0 +1,121 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +#include "k8t890.h" + +void mmconfig_set_resources(device_t dev) +{ + struct resource *resource; + u8 reg; + + resource = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (resource) { + report_resource_stored(dev, resource, "<mmconfig>"); + + /* Remember this resource has been stored. */ + resource->flags |= IORESOURCE_STORED; + pci_write_config8(dev, K8T890_MMCONFIG_MBAR, + (resource->base >> 28)); + reg = pci_read_config8(dev, 0x60); + reg |= 0x3; + /* Enable MMCONFIG decoding. */ + pci_write_config8(dev, 0x60, reg); + } + pci_dev_set_resources(dev); +} + +static void apic_mmconfig_read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, 0x40); + /* NB APIC fixed to this address. */ + res->base = K8T890_APIC_BASE; + res->size = 256; + res->limit = res->base + res->size - 1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Add an MMCONFIG resource. */ + res = new_resource(dev, K8T890_MMCONFIG_MBAR); + res->size = 256 * 1024 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void traf_ctrl_enable(struct device *dev) +{ + volatile u32 *apic; + u32 data; + + /* Enable D3F1-D3F3, no device2 redirect, enable just one device behind + * bridge device 2 and device 3). + */ + pci_write_config8(dev, 0x60, 0x88); + + /* Will enable MMCONFIG later. */ + pci_write_config8(dev, 0x64, 0x23); + /* No extended RCRB Base Address. */ + pci_write_config8(dev, 0x62, 0x00); + + /* Offset80 ->95 bit 4 in 1 in Award. */ + + /* Enable APIC, to K8T890_APIC_BASE. */ + pci_write_config8(dev, 0x41, 0x00); + pci_write_config8(dev, 0x40, 0x8c); + /* BT_INTR enable, APIC Nonshare Mode Enable. */ + pci_write_config8(dev, 0x42, 0x5); + + apic = (u32 *)K8T890_APIC_BASE; + + /* Set APIC to FSB transported messages. */ + apic[0] = 3; + data = apic[4]; + apic[4] = (data & 0xFFFFFE) | 1; + + /* Set APIC ID. */ + apic[0] = 0; + data = apic[4]; + apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24); +} + +static struct device_operations traf_ctrl_ops = { + .read_resources = apic_mmconfig_read_resources, + .set_resources = mmconfig_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = traf_ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &traf_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_5, +}; diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc new file mode 100644 index 0000000000..d4954e53a1 --- /dev/null +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -0,0 +1,61 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file constructs the ROM strap table for K8T890. */ + +.section ".romstrap", "a", @progbits + +.globl __romstrap_start +.globl __romstrap_end + +__romstrap_start: + +/* + * Below are some Dev0 Func2 HT control registers values, + * depending on strap pin, one of below lines is used. + */ +tblpointer: +.long 0x504400AA, 0x61970FC2 //;200M +.long 0x504400AA, 0x61970FC2 //;400M +.long 0x504400AA, 0x61970FC2 //;600M +.long 0x504400AA, 0x61970FC2 //;800M +.long 0x504400AA, 0x61970FC2 //;1000M +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +/* + * The pointer to above table should be at 0xffffd, + * the table itself MUST be aligned to 128B it seems! + */ +.long tblpointer - 0xFFF00000 + +__romstrap_end: + +.previous diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.lds new file mode 100644 index 0000000000..9a3574339c --- /dev/null +++ b/src/southbridge/via/k8t890/romstrap.lds @@ -0,0 +1,29 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu@amd.com> for AMD) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek@assembler.cz>. */ + +SECTIONS { + . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} |