diff options
Diffstat (limited to 'src/southbridge/via/vt8231')
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 6 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_acpi.c | 12 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_serial.c | 16 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_smbus.c | 4 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_ide.c | 38 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_lpc.c | 32 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_nic.c | 2 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231_usb.c | 20 |
8 files changed, 65 insertions, 65 deletions
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 43238ec050..85f007a097 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -18,7 +18,7 @@ static void keyboard_on(void) if (lpc_dev) { regval = pci_read_config8(lpc_dev, 0x51); - regval |= 0x0f; + regval |= 0x0f; pci_write_config8(lpc_dev, 0x51, regval); } pc_keyboard_init(0); @@ -27,9 +27,9 @@ static void keyboard_on(void) static void com_port_on(void) { #if 0 - // enable com1 and com2. + // enable com1 and com2. enables = pci_read_config8(dev, 0x6e); - + /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 * is enable com port a as com1 kevinh/Ispiri - Old code * thought 0x01 would make it com1, that was wrong enables = diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c index 6cbf4c591f..647910aef6 100644 --- a/src/southbridge/via/vt8231/vt8231_acpi.c +++ b/src/southbridge/via/vt8231/vt8231_acpi.c @@ -10,20 +10,20 @@ static void acpi_init(struct device *dev) // Set ACPI base address to IO 0x4000 pci_write_config32(dev, 0x48, 0x4001); - + // Enable ACPI access (and setup like award) pci_write_config8(dev, 0x41, 0x84); - + // Set hardware monitor base address to IO 0x6000 pci_write_config32(dev, 0x70, 0x6001); - + // Enable hardware monitor (and setup like award) pci_write_config8(dev, 0x74, 0x01); - + // set IO base address to 0x5000 pci_write_config32(dev, 0x90, 0x5001); - - // Enable SMBus + + // Enable SMBus pci_write_config8(dev, 0xd2, 0x01); } diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c index 5b38b8e521..af5a7729ee 100644 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -8,18 +8,18 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vt8231_writesuper(uint8_t reg, uint8_t val) +static void vt8231_writesuper(uint8_t reg, uint8_t val) { outb(reg, SIO_BASE); outb(val, SIO_DATA); } -static void vt8231_writesiobyte(uint16_t reg, uint8_t val) +static void vt8231_writesiobyte(uint16_t reg, uint8_t val) { outb(val, reg); } -static void vt8231_writesioword(uint16_t reg, uint16_t val) +static void vt8231_writesioword(uint16_t reg, uint16_t val) { outw(val, reg); } @@ -29,26 +29,26 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) mainboard */ -static void enable_vt8231_serial(void) +static void enable_vt8231_serial(void) { uint8_t c; device_t dev; outb(6, 0x80); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - + if (dev == PCI_DEV_INVALID) { outb(7, 0x80); die("Serial controller not found\n"); } - - /* first, you have to enable the superio and superio config. + + /* first, you have to enable the superio and superio config. put a 6 reg 80 */ c = pci_read_config8(dev, 0x50); c |= 6; pci_write_config8(dev, 0x50, c); outb(2, 0x80); - // now go ahead and set up com1. + // now go ahead and set up com1. // set address vt8231_writesuper(0xf4, 0xfe); // enable serial out diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c index 40ef656c00..8ba72a387b 100644 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c @@ -35,7 +35,7 @@ static void enable_smbus(void) // set IO base address to SMBUS_IO_BASE pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - // Enable SMBus + // Enable SMBus c = pci_read_config8(dev, 0xd2); c |= 5; pci_write_config8(dev, 0xd2, c); @@ -244,7 +244,7 @@ static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex) } #endif -/* for reference, here is the fancier version which we will use at some +/* for reference, here is the fancier version which we will use at some * point */ # if 0 diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c index c1df5ef5cd..46479c4af3 100644 --- a/src/southbridge/via/vt8231/vt8231_ide.c +++ b/src/southbridge/via/vt8231/vt8231_ide.c @@ -18,7 +18,7 @@ static void ide_init(struct device *dev) * or it is possibly a timing issue. Ben Hewson 29 Apr 2007. */ - /* + /* printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__); enables = pci_read_config8(dev, 0x42); printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); @@ -28,73 +28,73 @@ static void ide_init(struct device *dev) printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); */ } - + enables = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); enables |= 3; pci_write_config8(dev, 0x40, enables); enables = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); - + // Enable prefetch buffers enables = pci_read_config8(dev, 0x41); enables |= 0xf0; pci_write_config8(dev, 0x41, enables); - + // Lower thresholds (cause award does it) enables = pci_read_config8(dev, 0x43); enables &= ~0x0f; enables |= 0x05; pci_write_config8(dev, 0x43, enables); - + // PIO read prefetch counter (cause award does it) pci_write_config8(dev, 0x44, 0x18); - + // Use memory read multiple pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. + + // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // kevinh@ispiri.com - the standard linux drivers seem ass slow when // used in native mode - I've changed back to classic enables = pci_read_config8(dev, 0x9); printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. + // by the book, set the low-order nibble to 0xa. if (conf->enable_native_ide) { enables &= ~0xf; - // cf/cg silicon needs an 'f' here. + // cf/cg silicon needs an 'f' here. enables |= 0xf; } else { enables &= ~0x5; } - + pci_write_config8(dev, 0x9, enables); enables = pci_read_config8(dev, 0x9); printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. + + // standard bios sets master bit. enables = pci_read_config8(dev, 0x4); printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); enables |= 7; - + // No need for stepping - kevinh@ispiri.com enables &= ~0x80; - + pci_write_config8(dev, 0x4, enables); enables = pci_read_config8(dev, 0x4); printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); - + if (!conf->enable_native_ide) { // Use compatability mode - per award bios pci_write_config32(dev, 0x10, 0x0); pci_write_config32(dev, 0x14, 0x0); pci_write_config32(dev, 0x18, 0x0); pci_write_config32(dev, 0x1c, 0x0); - + // Force interrupts to use compat mode - just like Award bios pci_write_config8(dev, 0x3d, 00); pci_write_config8(dev, 0x3c, 0xff); - } + } } static struct device_operations ide_ops = { diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c index 6c517ff492..c874528dec 100644 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ b/src/southbridge/via/vt8231/vt8231_lpc.c @@ -25,7 +25,7 @@ static void pci_routing_fixup(struct device *dev) printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); if (dev) { /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D + on the PCB routing of PINTA-D PINTA = IRQ11 PINTB = IRQ5 @@ -61,60 +61,60 @@ static void vt8231_init(struct device *dev) enables = pci_read_config8(dev, 0x6C); enables |= 0x80; pci_write_config8(dev, 0x6C, enables); - + // Map 4MB of FLASH into the address space pci_write_config8(dev, 0x41, 0x7f); - + // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI // interrupts can be properly marked as level triggered. enables = pci_read_config8(dev, 0x40); pci_write_config8(dev, 0x40, enables); - + // Set 0x42 to 0xf0 to match Award bios enables = pci_read_config8(dev, 0x42); enables |= 0xf0; pci_write_config8(dev, 0x42, enables); - + // Set bit 3 of 0x4a, to match award (dummy pci request) enables = pci_read_config8(dev, 0x4a); enables |= 0x08; pci_write_config8(dev, 0x4a, enables); - + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); - + // Set 0x58 to 0x03 to match Award pci_write_config8(dev, 0x58, 0x03); - + // enable the ethernet/RTC if (dev) { enables = pci_read_config8(dev, 0x51); - enables |= 0x18; + enables |= 0x18; pci_write_config8(dev, 0x51, enables); } // enable IDE, since Linux won't do it. // First do some more things to devfn (17,0) - // note: this should already be cleared, according to the book. + // note: this should already be cleared, according to the book. enables = pci_read_config8(dev, 0x50); printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables); enables &= ~8; // need manifest constant here! printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables); pci_write_config8(dev, 0x50, enables); - + // set default interrupt values (IDE) enables = pci_read_config8(dev, 0x4c); printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. + // clear out whatever was there. enables &= ~0xf; enables |= 4; printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables); pci_write_config8(dev, 0x4c, enables); - - // set up the serial port interrupts. + + // set up the serial port interrupts. // com2 to 3, com1 to 4 pci_write_config8(dev, 0x46, 0x04); pci_write_config8(dev, 0x47, 0x03); @@ -123,7 +123,7 @@ static void vt8231_init(struct device *dev) /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); //ethernet_fixup(); - + // Start the rtc rtc_init(0); } diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c index d4771f6816..5cd6cd8ca1 100644 --- a/src/southbridge/via/vt8231/vt8231_nic.c +++ b/src/southbridge/via/vt8231/vt8231_nic.c @@ -5,7 +5,7 @@ #include <device/pci_ids.h> /* - * Enable the ethernet device and turn off stepping (because it is integrated + * Enable the ethernet device and turn off stepping (because it is integrated * inside the southbridge) */ static void nic_init(struct device *dev) diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c index 3dd0b4272b..e12a8db85a 100644 --- a/src/southbridge/via/vt8231/vt8231_usb.c +++ b/src/southbridge/via/vt8231/vt8231_usb.c @@ -9,7 +9,7 @@ static void usb_on(int enable) device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); /* USB controller 2 */ device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); - + /* enable USB1 */ if(dev2) { if (enable) { @@ -20,16 +20,16 @@ static void usb_on(int enable) pci_write_config8(dev2, 0x04, 0x00); } } - + if(dev0) { regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x10); + if (enable) + regval &= ~(0x10); else - regval |= 0x10; + regval |= 0x10; pci_write_config8(dev0, 0x50, regval); } - + /* enable USB2 */ if(dev3) { if (enable) { @@ -40,13 +40,13 @@ static void usb_on(int enable) pci_write_config8(dev3, 0x04, 0x00); } } - + if(dev0) { regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x20); + if (enable) + regval &= ~(0x20); else - regval |= 0x20; + regval |= 0x20; pci_write_config8(dev0, 0x50, regval); } } |