diff options
Diffstat (limited to 'src/southbridge/sis')
24 files changed, 0 insertions, 3351 deletions
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig deleted file mode 100644 index c6023a9998..0000000000 --- a/src/southbridge/sis/sis966/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config SOUTHBRIDGE_SIS_SIS966 - bool - select IOAPIC - select HAVE_USBDEBUG - select HAVE_HARD_RESET - -if SOUTHBRIDGE_SIS_SIS966 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/sis/sis966/bootblock.c" - -config EHCI_BAR - hex - default 0xfef00000 - -endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc deleted file mode 100644 index fa37762287..0000000000 --- a/src/southbridge/sis/sis966/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_SIS_SIS966),y) - -ramstage-y += sis761.c -ramstage-y += sis966.c -ramstage-y += lpc.c -ramstage-y += ide.c -ramstage-y += usb.c -ramstage-y += usb2.c -ramstage-y += nic.c -ramstage-y += sata.c -ramstage-y += pcie.c -ramstage-y += aza.c -ramstage-y += reset.c - -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c - -bootblock-y += romstrap.ld -bootblock-y += romstrap.S - -endif diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c deleted file mode 100644 index 39bc675f6b..0000000000 --- a/src/southbridge/sis/sis966/aza.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> -#include <delay.h> -#include "sis966.h" - -u8 SiS_SiS7502_init[7][3]={ -{0x04, 0xFF, 0x07}, -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x91}, -{0x2F, 0xFF, 0x01}, -{0x04, 0xFF, 0x06}, -{0x00, 0x00, 0x00} //End of table -}; - -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 dword; - int count; - - val &= mask; - dword = read32(port); - dword &= ~mask; - dword |= val; - write32(port, dword); - - count = 50; - do { - dword = read32(port); - dword &= mask; - udelay(100); - } while ((dword != val) && --count); - - if (!count) return -1; - - udelay(500); - return 0; - -} - -static u32 send_verb(u8 *base, u32 verb) -{ - u32 dword; - - dword = read32(base + 0x68); - dword = dword|(unsigned long)0x0002; - write32(base + 0x68, dword); - do { - dword = read32(base + 0x68); - } while ((dword & 1) != 0); - write32(base + 0x60, verb); - udelay(500); - dword = read32(base + 0x68); - dword = (dword |0x1); - write32(base + 0x68, dword); - do { - udelay(100); - dword = read32(base + 0x68); - } while ((dword & 3) != 2); - - dword = read32(base + 0x64); - return dword; -} - - -static int codec_detect(u8 *base) -{ - u32 dword; - int idx = 0; - - /* 1 */ // controller reset - printk(BIOS_DEBUG, "controller reset\n"); - - set_bits(base + 0x08, 1, 1); - - do { - dword = read32(base + 0x08)&0x1; - if (idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;} - } while (dword !=1); - - dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId - - if (dword == 0) { - printk(BIOS_DEBUG, "No codec!\n"); - return 0; - } - - printk(BIOS_DEBUG, "Codec ID = %x\n", dword); - - dword = 0x1; - return dword; - -} - - -static u32 verb_data[] = { - -//14 - 0x01471c10, - 0x01471d40, - 0x01471e01, - 0x01471f01, -//15 - 0x01571c12, - 0x01571d10, - 0x01571e01, - 0x01571f01, -//16 - 0x01671c11, - 0x01671d60, - 0x01671e01, - 0x01671f01, -//17 - 0x01771c14, - 0x01771d20, - 0x01771e01, - 0x01771f01, -//18 - 0x01871c40, - 0x01871d98, - 0x01871ea1, - 0x01871f01, -//19 - 0x01971c50, - 0x01971d98, - 0x01971ea1, - 0x01971f02, -//1a - 0x01a71c4f, - 0x01a71d30, - 0x01a71e81, - 0x01a71f01, -//1b - 0x01b71c20, - 0x01b71d40, - 0x01b71e01, - 0x01b71f02, -//1c - 0x01c71cf0, - 0x01c71d01, - 0x01c71e33, - 0x01c71f59, -//1d - 0x01d71c01, - 0x01d71de6, - 0x01d71e05, - 0x01d71f40, -//1e - 0x01e71c30, - 0x01e71d11, - 0x01e71e44, - 0x01e71f01, -//1f - 0x01f71c60, - 0x01f71d61, - 0x01f71ec4, - 0x01f71f01, -}; - -static unsigned find_verb(u32 viddid, u32 **verb) -{ - if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; - *verb = (u32 *)verb_data; - return sizeof(verb_data)/sizeof(u32); -} - - -static void codec_init(u8 *base, int addr) -{ - u32 dword; - u32 *verb; - unsigned verb_size; - int i; - - /* 1 */ - do { - dword = read32(base + 0x68); - } while (dword & 1); - - dword = (addr << 28) | 0x000f0000; - write32(base + 0x60, dword); - - do { - dword = read32(base + 0x68); - } while ((dword & 3) != 2); - - dword = read32(base + 0x64); - - /* 2 */ - printk(BIOS_DEBUG, "codec viddid: %08x\n", dword); - verb_size = find_verb(dword, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "No verb!\n"); - return; - } - - printk(BIOS_DEBUG, "verb_size: %d\n", verb_size); - /* 3 */ - for (i=0; i<verb_size; i++) { - send_verb(base,verb[i]); - } - printk(BIOS_DEBUG, "verb loaded!\n"); -} - -static void codecs_init(u8 *base, u32 codec_mask) -{ - codec_init(base, 0); - return; -} - -static void aza_init(struct device *dev) -{ - u8 *base; - struct resource *res; - u32 codec_mask; - - printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n"); - -//-------------- enable AZA (SiS7502) ------------------------- -{ - u8 temp8; - int i=0; - while (SiS_SiS7502_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); - temp8 &= SiS_SiS7502_init[i][1]; - temp8 |= SiS_SiS7502_init[i][2]; - pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); - i++; - }; -} -//----------------------------------------------------------- - - - // put audio to D0 state - pci_write_config8(dev, 0x54,0x00); - -#if DEBUG_AZA -{ - int i; - - printk(BIOS_DEBUG, "****** Azalia PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i=0; i<0xff; i+=4){ - if ((i%16)==0){ - printk(BIOS_DEBUG, "\n%02x: ", i); - } - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); -} -#endif - - res = find_resource(dev, 0x10); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "base = 0x%p\n", base); - - codec_mask = codec_detect(base); - - if (codec_mask) { - printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); - } - - printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations aza_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -// .enable = sis966_enable, - .init = aza_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver azaaudio_driver __pci_driver = { - .ops = &aza_audio_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_HD_AUDIO, -}; diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c deleted file mode 100644 index 670ff251b1..0000000000 --- a/src/southbridge/sis/sis966/bootblock.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ids.h> -#include "sis966.h" - -static void sis966_enable_rom(void) -{ - pci_devfn_t addr; - - /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ - addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, - PCI_DEVICE_ID_SIS_SIS966_LPC), 0); - - /* Set the 4MB enable bit(s). */ - pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); -} - -static void bootblock_southbridge_init(void) -{ - sis966_enable_rom(); -} diff --git a/src/southbridge/sis/sis966/chip.h b/src/southbridge/sis/sis966/chip.h deleted file mode 100644 index a148f68cba..0000000000 --- a/src/southbridge/sis/sis966/chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SIS966_CHIP_H -#define SIS966_CHIP_H - -struct southbridge_sis_sis966_config -{ - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; -}; - -#endif /* SIS966_CHIP_H */ diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c deleted file mode 100644 index 4fb2d9d11b..0000000000 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> - -static unsigned get_sbdn(unsigned bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), - bus); - - return (dev>>15) & 0x1f; -} - -void do_hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) -{ - /* default value for sis966 is good */ - /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ -} - -void do_soft_reset(void) -{ - set_bios_reset(); - - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); - -} diff --git a/src/southbridge/sis/sis966/early_setup_car.c b/src/southbridge/sis/sis966/early_setup_car.c deleted file mode 100644 index 624a68f577..0000000000 --- a/src/southbridge/sis/sis966/early_setup_car.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) -{ - uint32_t tgio_ctrl; - uint32_t pll_ctrl; - uint32_t dword; - int i; - pci_devfn_t dev; - dev = PCI_DEV(busnx, devnx+1, 1); - dword = pci_read_config32(dev, 0xe4); - dword |= 0x3f0; // disable it at first - pci_write_config32(dev, 0xe4, dword); - - for (i=0; i<3; i++) { - tgio_ctrl = inl(anactrl_io_base + 0xcc); - tgio_ctrl &= ~(3<<9); - tgio_ctrl |= (i<<9); - outl(tgio_ctrl, anactrl_io_base + 0xcc); - pll_ctrl = inl(anactrl_io_base + 0x30); - pll_ctrl |= (1<<31); - outl(pll_ctrl, anactrl_io_base + 0x30); - do { - pll_ctrl = inl(anactrl_io_base + 0x30); - } while (!(pll_ctrl & 1)); - } - tgio_ctrl = inl(anactrl_io_base + 0xcc); - tgio_ctrl &= ~((7<<4)|(1<<8)); - tgio_ctrl |= (pci_e_x<<4)|(1<<8); - outl(tgio_ctrl, anactrl_io_base + 0xcc); - -// wait 100us - udelay(100); - - dword = pci_read_config32(dev, 0xe4); - dword &= ~(0x3f0); // enable - pci_write_config32(dev, 0xe4, dword); - -// need to wait 100ms - mdelay(100); -} diff --git a/src/southbridge/sis/sis966/early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h deleted file mode 100644 index afb1a31969..0000000000 --- a/src/southbridge/sis/sis966/early_setup_ss.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static const unsigned int pcie_ss_tbl[] = { - 0x0C504103f, - 0x0C504103f, - 0x0C504103f, - 0x0C5042040, - 0x0C5042040, - 0x0C5042040, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5043041, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5049047, - 0x0C5049047, - 0x0C5049047, - 0x0C504a048, - 0x0C504a048, - 0x0C504b049, - 0x0C504b049, - 0x0C504a048, - 0x0C504a048, - 0x0C5049047, - 0x0C5049047, - 0x0C5048046, - 0x0C5048046, - 0x0C5048046, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5047045, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5046044, - 0x0C5045043, - 0x0C5045043, - 0x0C5045043, - 0x0C5044042, - 0x0C5044042, - 0x0C5044042, - 0x0C5043041, - 0x0C5043041, - 0x0C5042040, - 0x0C5042040, -}; -static const unsigned int sata_ss_tbl[] = { - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904b049, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c904a048, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9049047, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9048046, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9047045, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9046044, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9045043, - 0x0c9044042, - 0x0c9044042, - 0x0c9044042, -}; - -static const unsigned int cpu_ss_tbl[] = { - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5034032, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5035033, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5036034, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5037035, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5038036, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503b039, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C503a038, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, - 0x0C5039037, -}; diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c deleted file mode 100644 index 3c8998ecfb..0000000000 --- a/src/southbridge/sis/sis966/early_smbus.c +++ /dev/null @@ -1,739 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "smbus.h" - -#define SMBUS0_IO_BASE 0x8D0 - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { - return 0; - } - outb(val,smbus_io_base + SMBHSTSTAT); - } while (--loops); - return -2; -} - -int smbus_wait_until_done(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(smbus_io_base + 0x00); - if ( (val & 0xff) != 0x02) { - return 0; - } - } while (--loops); - return -3; -} - -int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned char global_status_register; - unsigned char byte; - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; -} - -int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} - -static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - outb(0xff, smbus_io_base + 0x00); - smbus_delay(); - outb(0x20, smbus_io_base + 0x03); - smbus_delay(); - - outb(((device & 0x7f) << 1)|1 , smbus_io_base + 0x04); - smbus_delay(); - outb(address & 0xff, smbus_io_base + 0x05); - smbus_delay(); - outb(0x12, smbus_io_base + 0x03); - smbus_delay(); - - int i, j; - for (i = 0;i < 0x1000; i++) { - if (inb(smbus_io_base + 0x00) != 0x08) { - smbus_delay(); - for (j=0;j<0xFFFF;j++); - } - } - - global_status_register = inb(smbus_io_base + 0x00); - byte = inb(smbus_io_base + 0x08); - - if (global_status_register != 0x08) { // lose check, otherwise it should be 0 - printk(BIOS_DEBUG, "Fail\r\t"); - return -1; - } - printk(BIOS_DEBUG, "Success\r\t"); - return byte; -} - - -static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); - - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - smbus_delay(); - - /* set up for a byte data write */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - - if (global_status_register != 0x80) { - return -1; - } - return 0; -} - - - -static const uint8_t SiS_LPC_init[34][3]={ -{0x04, 0xF8, 0x07}, //Reg 0x04 -{0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash -{0x46, 0x00, 0x3D}, //Reg 0x46 -{0x47, 0x00, 0xDD}, //Reg 0x47 -{0x48, 0x00, 0x12}, //Reg 0x48 -{0x64, 0x00, 0xFF}, //Reg 0x64 -{0x65, 0x00, 0xC1}, //Reg 0x65 -{0x68, 0x00, 0x89}, //Reg 0x68 //SB.ASM, START POST -{0x69, 0x00, 0x80}, //Reg 0x69 -{0x6B, 0x00, 0x00}, //Reg 0x6B //SBBB.ASM -{0x6C, 0xFF, 0x97}, //Reg 0x6C //SBBB.ASM -{0x6E, 0x00, 0x00}, //Reg 0x6E //SBBB.ASM But in Early Post sets 0x04. -{0x6F, 0xFF, 0x14}, //Reg 0x6F //SBBB.ASM -{0x77, 0x00, 0x0E}, //Reg 0x77 //SBOEM.ASM, EARLY POST -{0x78, 0x00, 0x20}, //Reg 0x78 -{0x7B, 0x00, 0x88}, //Reg 0x7B -{0x7F, 0x00, 0x40}, //Reg 0x7F //SBOEM.ASM, EARLY POST -{0xC1, 0x00, 0xF0}, //Reg 0xC1 -{0xC2, 0x00, 0x01}, //Reg 0xC2 -{0xC3, 0x00, 0x00}, //Reg 0xC3 //NBAGPBB.ASM -{0xC9, 0x00, 0x80}, //Reg 0xC9 -{0xCF, 0x00, 0x45}, //Reg 0xCF -{0xD0, 0x00, 0x02}, //Reg 0xD0 -{0xD4, 0x00, 0x44}, //Reg 0xD4 -{0xD5, 0x00, 0x62}, //Reg 0xD5 -{0xD6, 0x00, 0x32}, //Reg 0xD6 -{0xD8, 0x00, 0x45}, //Reg 0xD8 -{0xDA, 0x00, 0xDA}, //Reg 0xDA -{0xDB, 0x00, 0x61}, //Reg 0xDB -{0xDC, 0x00, 0xAA}, //Reg 0xDC -{0xDD, 0x00, 0xAA}, //Reg 0xDD -{0xDE, 0x00, 0xAA}, //Reg 0xDE -{0xDF, 0x00, 0xAA}, //Reg 0xDF -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_NBPCIE_init[43][3]={ -{0x3D, 0x00, 0x00}, //Reg 0x3D -{0x1C, 0xFE, 0x01}, //Reg 0x1C -{0x1D, 0xFE, 0x01}, //Reg 0x1D -{0x24, 0xFE, 0x01}, //Reg 0x24 -{0x26, 0xFE, 0x01}, //Reg 0x26 -{0x40, 0xFF, 0x10}, //Reg 0x40 -{0x43, 0xFF, 0x78}, //Reg 0x43 -{0x44, 0xFF, 0x02}, //Reg 0x44 -{0x45, 0xFF, 0x10}, //Reg 0x45 -{0x48, 0xFF, 0x52}, //Reg 0x48 -{0x49, 0xFF, 0xE3}, //Reg 0x49 -{0x5A, 0x00, 0x00}, //Reg 0x4A -{0x4B, 0x00, 0x16}, //Reg 0x4B -{0x4C, 0x00, 0x80}, //Reg 0x4C -{0x4D, 0x00, 0x02}, //Reg 0x4D -{0x4E, 0x00, 0x00}, //Reg 0x4E -{0x5C, 0x00, 0x52}, //Reg 0x5C -{0x5E, 0x00, 0x10}, //Reg 0x5E -{0x34, 0x00, 0xD0}, //Reg 0x34 -{0xD0, 0x00, 0x01}, //Reg 0xD0 -{0x4F, 0x00, 0x80}, //Reg 0x4F -{0xA1, 0x00, 0xF4}, //Reg 0xA1 -{0xA2, 0x7F, 0x00}, //Reg 0xA2 -{0xBD, 0x00, 0xA0}, //Reg 0xBD -{0xD1, 0xFF, 0x00}, //Reg 0xD1 -{0xD3, 0xFE, 0x01}, //Reg 0xD3 -{0xD4, 0x18, 0x20}, //Reg 0xD4 -{0xD5, 0xF0, 0x00}, //Reg 0xD5 -{0xDD, 0xFF, 0x00}, //Reg 0xDD -{0xDE, 0xEC, 0x10}, //Reg 0xDE -{0xDF, 0xFF, 0x00}, //Reg 0xDF -{0xE0, 0xF7, 0x00}, //Reg 0xE0 -{0xE3, 0xEF, 0x10}, //Reg 0xE3 -{0xE4, 0x7F, 0x80}, //Reg 0xE4 -{0xE5, 0xFF, 0x00}, //Reg 0xE5 -{0xE6, 0x06, 0x00}, //Reg 0xE6 -{0xE7, 0xFF, 0x00}, //Reg 0xE7 -{0xF5, 0x00, 0x00}, //Reg 0xF5 -{0xF6, 0x3F, 0x00}, //Reg 0xF6 -{0xF7, 0xFF, 0x00}, //Reg 0xF7 -{0xFD, 0xFF, 0x00}, //Reg 0xFD -{0x4F, 0x00, 0x00}, //Reg 0x4F -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_ACPI_init[10][3]={ -{0x1B, 0xBF, 0x40}, //Reg 0x1B -{0x84, 0x00, 0x0E}, //Reg 0x84 -{0x85, 0x00, 0x29}, //Reg 0x85 -{0x86, 0x00, 0xCB}, //Reg 0x86 -{0x87, 0x00, 0x55}, //Reg 0x87 -{0x6B, 0x00, 0x00}, //Reg 0x6B -{0x6C, 0x68, 0x97}, //Reg 0x6C -{0x6E, 0x00, 0x00}, //Reg 0x6E -{0x6F, 0xFF, 0x14}, //Reg 0x6F -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_SBPCIE_init[13][3]={ -{0x48, 0x00 ,0x07}, //Reg 0x48 -{0x49, 0x00 ,0x06}, //Reg 0x49 -{0x4A, 0x00 ,0x0C}, //Reg 0x4A -{0x4B, 0x00 ,0x00}, //Reg 0x4B -{0x4E, 0x00 ,0x20}, //Reg 0x4E -{0x1C, 0x00 ,0xF1}, //Reg 0x1C -{0x1D, 0x00 ,0x01}, //Reg 0x1D -{0x24, 0x00 ,0x01}, //Reg 0x24 -{0x26, 0x00 ,0x01}, //Reg 0x26 -{0xF6, 0x00 ,0x02}, //Reg 0xF6 -{0xF7, 0x00 ,0xC8}, //Reg 0xF7 -{0x5B, 0x00 ,0x40}, //Reg 0x5B -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_NB_init[56][3]={ -{0x04, 0x00 ,0x07}, //Reg 0x04 -{0x05, 0x00 ,0x00}, //Reg 0x05 // alex -{0x0D, 0x00 ,0x20}, //Reg 0x0D -{0x2C, 0x00 ,0x39}, //Reg 0x2C -{0x2D, 0x00 ,0x10}, //Reg 0x2D -{0x2E, 0x00 ,0x61}, //Reg 0x2E -{0x2F, 0x00 ,0x07}, //Reg 0x2F -{0x34, 0x00 ,0xA0}, //Reg 0x34 -{0x40, 0x00 ,0x36}, //Reg 0x40 -{0x42, 0x00 ,0xB9}, //Reg 0x42 -{0x43, 0x00 ,0x8B}, //Reg 0x43 -{0x44, 0x00 ,0x05}, //Reg 0x44 -{0x45, 0x00 ,0xFF}, //Reg 0x45 -{0x46, 0x00 ,0x90}, //Reg 0x46 -{0x47, 0x00 ,0xA0}, //Reg 0x47 -//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable -{0x4E, 0x00 ,0x00}, //Reg 0x4E -{0x4F, 0x00 ,0x02}, //Reg 0x4F -{0x5B, 0x00 ,0x44}, //Reg 0x5B -{0x5D, 0x00 ,0x00}, //Reg 0x5D -{0x5E, 0x00 ,0x25}, //Reg 0x5E -{0x61, 0x00 ,0xB0}, //Reg 0x61 -{0x65, 0x00 ,0xB0}, //Reg 0x65 -{0x68, 0x00 ,0x4C}, //Reg 0x68 -{0x69, 0x00 ,0xD0}, //Reg 0x69 -{0x6B, 0x00 ,0x07}, //Reg 0x6B -{0x6C, 0x00 ,0xDD}, //Reg 0x6C -{0x6D, 0x00 ,0xAD}, //Reg 0x6D -{0x6E, 0x00 ,0xE8}, //Reg 0x6E -{0x6F, 0x00 ,0x4D}, //Reg 0x6F -{0x70, 0x00 ,0x00}, //Reg 0x70 -{0x71, 0x00 ,0x80}, //Reg 0x71 -{0x72, 0x00 ,0x00}, //Reg 0x72 -{0x73, 0x00 ,0x00}, //Reg 0x73 -{0x74, 0x00 ,0x01}, //Reg 0x74 -{0x75, 0x00 ,0x10}, //Reg 0x75 -{0x7E, 0x00 ,0x29}, //Reg 0x7E -{0x8B, 0x00 ,0x10}, //Reg 0x8B -{0x8D, 0x00 ,0x03}, //Reg 0x8D -{0xA1, 0x00 ,0xD0}, //Reg 0xA1 -{0xA2, 0x00 ,0x30}, //Reg 0xA2 -{0xA4, 0x00 ,0x0B}, //Reg 0xA4 -{0xA9, 0x00 ,0x02}, //Reg 0xA9 -{0xB0, 0x00 ,0x30}, //Reg 0xB0 -{0xB4, 0x00 ,0x30}, //Reg 0xB4 -{0x90, 0x00 ,0x00}, //Reg 0x90 -{0x91, 0x00 ,0x00}, //Reg 0x91 -{0x92, 0x00 ,0x00}, //Reg 0x92 -{0x93, 0x00 ,0x00}, //Reg 0x93 -{0x94, 0x00 ,0x00}, //Reg 0x94 -{0x95, 0x00 ,0x00}, //Reg 0x95 -{0x96, 0x00 ,0x00}, //Reg 0x96 -{0x97, 0x00 ,0x00}, //Reg 0x97 -{0x98, 0x00 ,0x00}, //Reg 0x98 -{0x99, 0x00 ,0x00}, //Reg 0x99 -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_NBAGP_init[34][3]={ -{0xCF, 0xDF, 0x00}, //HT issue -{0x06, 0xDF, 0x20}, -{0x1E, 0xDF, 0x20}, -{0x50, 0x00, 0x02}, -{0x51, 0x00, 0x00}, -{0x54, 0x00, 0x09}, -{0x55, 0x00, 0x00}, -{0x56, 0x00, 0x80}, -{0x58, 0x00, 0x08}, -{0x60, 0x00, 0xB1}, -{0x61, 0x00, 0x02}, -{0x62, 0x00, 0x60}, -{0x63, 0x00, 0x60}, -{0x64, 0x00, 0xAA}, -{0x65, 0x00, 0x18}, -{0x68, 0x00, 0x23}, -{0x69, 0x00, 0x23}, -{0x6A, 0x00, 0xC8}, -{0x6B, 0x00, 0x08}, -{0x6C, 0x00, 0x00}, -{0x6D, 0x00, 0x00}, -{0x6E, 0x00, 0x08}, -{0x6F, 0x00, 0x00}, -{0xBB, 0x00, 0x00}, -{0xB5, 0x00, 0x30}, -{0xB0, 0x00, 0xDB}, -{0xB6, 0x00, 0x73}, -{0xB7, 0x00, 0x50}, -{0xBA, 0xBF, 0x41}, -{0xB4, 0x3F, 0xC0}, -{0xBF, 0xF9, 0x06}, -{0xBA, 0x00, 0x61}, -{0xBD, 0x7F, 0x80}, -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_ACPI_2_init[56][3]={ -{0x00, 0x00, 0xFF}, //Reg 0x00 -{0x01, 0x00, 0xFF}, //Reg 0x01 -{0x02, 0x00, 0x00}, //Reg 0x02 -{0x03, 0x00, 0x00}, //Reg 0x03 -{0x16, 0x00, 0x00}, //Reg 0x16 -{0x20, 0x00, 0xFF}, //Reg 0x20 -{0x21, 0x00, 0xFF}, //Reg 0x21 -{0x22, 0x00, 0x00}, //Reg 0x22 -{0x23, 0x00, 0x00}, //Reg 0x23 -{0x24, 0x00, 0x55}, //Reg 0x24 -{0x25, 0x00, 0x55}, //Reg 0x25 -{0x26, 0x00, 0x55}, //Reg 0x26 -{0x27, 0x00, 0x55}, //Reg 0x27 -{0x2A, 0x00, 0x40}, //Reg 0x2A -{0x2B, 0x00, 0x10}, //Reg 0x2B -{0x2E, 0x00, 0xFF}, //Reg 0x2E -{0x30, 0x00, 0xFF}, //Reg 0x30 -{0x31, 0x00, 0xFF}, //Reg 0x31 -{0x32, 0x00, 0x00}, //Reg 0x32 -{0x33, 0x00, 0x00}, //Reg 0x33 -{0x40, 0x00, 0xFF}, //Reg 0x40 -{0x41, 0x00, 0xFF}, //Reg 0x41 -{0x42, 0x00, 0x00}, //Reg 0x42 -{0x43, 0x00, 0x00}, //Reg 0x43 -{0x4A, 0x00, 0x00}, //Reg 0x4A -{0x4E, 0x00, 0x0F}, //Reg 0x4E -{0x5A, 0x00, 0x00}, //Reg 0x5A -{0x5B, 0x00, 0x00}, //Reg 0x5B -{0x62, 0x00, 0x00}, //Reg 0x62 -{0x63, 0x00, 0x04}, //Reg 0x63 -{0x68, 0x00, 0xFF}, //Reg 0x68 -{0x76, 0x00, 0xA0}, //Reg 0x76 -{0x77, 0x00, 0x22}, //Reg 0x77 -{0x78, 0xDF, 0x20}, //Reg 0x78 -{0x7A, 0x00, 0x10}, //Reg 0x7A -{0x7C, 0x00, 0x45}, //Reg 0x7C -{0x7D, 0x00, 0xB8}, //Reg 0x7D -{0x7F, 0x00, 0x00}, //Reg 0x7F -{0x80, 0x00, 0x1C}, //Reg 0x80 -{0x82, 0x00, 0x01}, //Reg 0x82 -{0x84, 0x00, 0x0E}, //Reg 0x84 -{0x85, 0x00, 0x29}, //Reg 0x85 -{0x86, 0x00, 0xCB}, //Reg 0x86 -{0x87, 0x00, 0x55}, //Reg 0x87 -{0x88, 0x00, 0x04}, //Reg 0x88 -{0x96, 0x00, 0x80}, //Reg 0x96 -{0x99, 0x00, 0x80}, //Reg 0x99 -{0x9A, 0x00, 0x15}, //Reg 0x9A -{0x9D, 0x00, 0x05}, //Reg 0x9D -{0x9E, 0x00, 0x00}, //Reg 0x9E -{0x9F, 0x00, 0x04}, //Reg 0x9F -{0xB0, 0x00, 0x6D}, //Reg 0xB0 -{0xB1, 0x00, 0x8C}, //Reg 0xB1 -{0xB9, 0x00, 0xFF}, //Reg 0xB9 -{0xBA, 0x00, 0x3F}, //Reg 0xBA -{0x00, 0x00, 0x00} //End of table -}; - -static const uint8_t SiS_SiS1183_init[44][3]={ -{0x04, 0x00, 0x05}, -{0x09, 0x00, 0x05}, -{0x2C, 0x00, 0x39}, -{0x2D, 0x00, 0x10}, -{0x2E, 0x00, 0x83}, -{0x2F, 0x00, 0x11}, -{0x90, 0x00, 0x40}, -{0x91, 0x00, 0x00}, // set mode -{0x50, 0x00, 0xA2}, -{0x52, 0x00, 0xA2}, -{0x55, 0x00, 0x96}, -{0x52, 0x00, 0xA2}, -{0x55, 0xF7, 0x00}, -{0x56, 0x00, 0xC0}, -{0x57, 0x00, 0x14}, -{0x67, 0x00, 0x28}, -{0x81, 0x00, 0xB3}, -{0x82, 0x00, 0x72}, -{0x83, 0x00, 0x40}, -{0x85, 0x00, 0xB3}, -{0x86, 0x00, 0x72}, -{0x87, 0x00, 0x40}, -{0x88, 0x00, 0xDE}, // after set mode -{0x89, 0x00, 0xB3}, -{0x8A, 0x00, 0x72}, -{0x8B, 0x00, 0x40}, -{0x8C, 0x00, 0xDE}, -{0x8D, 0x00, 0xB3}, -{0x8E, 0x00, 0x92}, -{0x8F, 0x00, 0x40}, -{0x93, 0x00, 0x00}, -{0x94, 0x00, 0x80}, -{0x95, 0x00, 0x08}, -{0x96, 0x00, 0x80}, -{0x97, 0x00, 0x08}, -{0x9C, 0x00, 0x80}, -{0x9D, 0x00, 0x08}, -{0x9E, 0x00, 0x80}, -{0x9F, 0x00, 0x08}, -{0xA0, 0x00, 0x15}, -{0xA1, 0x00, 0x15}, -{0xA2, 0x00, 0x15}, -{0xA3, 0x00, 0x15}, -{0x00, 0x00, 0x00} //End of table -}; - -/* In => Share Memory size - * => 00h : 0MBytes - * => 02h : 32MBytes - * => 03h : 64MBytes - * => 03h : 64MBytes - * => 04h : 128MBytes - * => Others: Reserved - */ -static void Init_Share_Memory(uint8_t ShareSize) -{ - pci_devfn_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, - PCI_DEVICE_ID_SIS_SIS761), 0); - pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | - (ShareSize << 5)); -} - -/* In: => Aperture size - * => 00h : 32MBytes - * => 01h : 64MBytes - * => 02h : 128MBytes - * => 03h : 256MBytes - * => 04h : 512MBytes - * => Others: Reserved - */ -static void Init_Aper_Size(uint8_t AperSize) -{ - pci_devfn_t dev; - uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); - pci_write_config8(dev, 0x90, AperSize << 1); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); -} - -static void sis_init_stage1(void) -{ - pci_devfn_t dev; - uint8_t temp8; - int i; - uint8_t GUI_En; - -// SiS_Chipset_Initialization -// ========================== NB ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - i=0; - while (SiS_NB_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_NB_init[i][0]); - temp8 &= SiS_NB_init[i][1]; - temp8 |= SiS_NB_init[i][2]; - pci_write_config8(dev, SiS_NB_init[i][0], temp8); - i++; - }; - -// ========================== LPC ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); - i=0; - while (SiS_LPC_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]); - temp8 &= SiS_LPC_init[i][1]; - temp8 |= SiS_LPC_init[i][2]; - pci_write_config8(dev, SiS_LPC_init[i][0], temp8); - i++; - }; -// ========================== ACPI ============================= - i=0; - while (SiS_ACPI_init[i][0] != 0) { - temp8 = inb(0x800 + SiS_ACPI_init[i][0]); - temp8 &= SiS_ACPI_init[i][1]; - temp8 |= SiS_ACPI_init[i][2]; - outb(temp8, 0x800 + SiS_ACPI_init[i][0]); - i++; - }; -// ========================== NBPCIE ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit - temp8 = pci_read_config8(dev, 0x4C); - GUI_En = temp8 & 0x10; - pci_write_config8(dev, 0x4C, temp8 & (~0x10)); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0); - i=0; - while (SiS_NBPCIE_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]); - temp8 &= SiS_NBPCIE_init[i][1]; - temp8 |= SiS_NBPCIE_init[i][2]; - pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8); - i++; - }; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit - temp8 = pci_read_config8(dev, 0x4C); - pci_write_config8(dev, 0x4C, temp8 | GUI_En); - - return; -} - - - -static void sis_init_stage2(void) -{ - pci_devfn_t dev; - msr_t msr; - int i; - uint8_t temp8; - uint16_t temp16; - - -// ========================== NB_AGP ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit - pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); - i=0; - - while (SiS_NBAGP_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); - temp8 &= SiS_NBAGP_init[i][1]; - temp8 |= SiS_NBAGP_init[i][2]; - pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); - i++; - }; - -/** - * Share Memory size - * => 00h : 0MBytes - * => 02h : 32MBytes - * => 03h : 64MBytes - * => 04h : 128MBytes - * => Others: Reserved - * - * Aperture size - * => 00h : 32MBytes - * => 01h : 64MBytes - * => 02h : 128MBytes - * => 03h : 256MBytes - * => 04h : 512MBytes - * => Others: Reserved - */ - - Init_Share_Memory(0x02); //0x02 : 32M - Init_Aper_Size(0x01); //0x1 : 64M - -// ========================== NB ============================= - - printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - msr = rdmsr(0xC001001A); - printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo ); - - temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; - temp16=0x0001<<(temp16-1); - temp16<<=8; - - printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); - pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); - pci_write_config8(dev, 0x7F, 0x08); // ACPI Base - outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function - -// ========================== ACPI ============================= - i=0; - printk(BIOS_DEBUG, "Init ACPI -------->\n"); - do { - temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]); - temp8 &= SiS_ACPI_2_init[i][1]; - temp8 |= SiS_ACPI_2_init[i][2]; - outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]); - i++; - } while (SiS_ACPI_2_init[i][0] != 0); - -// ========================== Misc ============================= - printk(BIOS_DEBUG, "Init Misc -------->\n"); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); - - /* R77h Internal PCI Device Enable 1 (Power On Value = 0h) - * bit5 : USB Emulation (1=enable) - * bit3 : Internal Keyboard Controller Port Access Control enable (1=enable) - * bit2 : Reserved - * bit1 : Mask USB A20M# Event (1:K8, 0:P4/K7) - */ - pci_write_config8(dev, 0x77, 0x2E); - - /* R7Ch Internal PCI Device Enable 2 (Power On Value = 0h) - * bit4 : SATA Controller Enable (0=enable) - * bit3 : IDE Controller Enable (0=enable) - * bit2 : MAC Controller Enable (0=enable) - * bit1 : MODEM Controller Enable (1=disable) - * bit0 : AC97 Controller Enable (1=disable) - */ - pci_write_config8(dev, 0x7C, 0x03); - - /* R7Eh Enable Azalia (Power On Value = 08h) - * bit3 : Azalia Controller Enable (0=enable) - */ - pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable - temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97 - outb(temp8, 0x878); // ACPI select AC97 or HDA controller - printk(BIOS_DEBUG, "Audio select %x\n",inb(0x878)); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0); - - if (!dev) - printk(BIOS_DEBUG, "SiS 1183 does not exist !!"); - // SATA Set Mode - pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40); - -} - - - -static void enable_smbus(void) -{ - pci_devfn_t dev; - uint8_t temp8; - printk(BIOS_DEBUG, "enable_smbus -------->\n"); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); - - /* set smbus iobase && enable ACPI Space*/ - pci_write_config16(dev, 0x74, 0x0800); // Set ACPI Base - temp8=pci_read_config8(dev, 0x40); // Enable ACPI Space - pci_write_config8(dev, 0x40, temp8 | 0x80); - temp8=pci_read_config8(dev, 0x76); // Enable SMBUS - pci_write_config8(dev, 0x76, temp8 | 0x03); - - printk(BIOS_DEBUG, "enable_smbus <--------\n"); -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); -} -int smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); -} diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c deleted file mode 100644 index 6be115e3e5..0000000000 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* TODO: Check whether this actually works (might be copy-paste leftover). */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ehci.h> -#include <device/pci_def.h> -#include "sis966.h" - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - return PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 dword; - - /* Write the port number to 0x74[15:12]. */ - dword = pci_read_config32(dev, 0x74); - dword &= ~(0xf << 12); - dword |= (port << 12); - pci_write_config32(dev, 0x74, dword); -} diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c deleted file mode 100644 index 716193c168..0000000000 --- a/src/southbridge/sis/sis966/ide.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> -#include "sis966.h" -#include "chip.h" - -uint8_t SiS_SiS5513_init[49][3]={ -{0x04, 0xFF, 0x05}, -{0x0D, 0xFF, 0x80}, -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x13}, -{0x2F, 0xFF, 0x55}, -{0x50, 0xFF, 0xA2}, -{0x51, 0xFF, 0x21}, -{0x53, 0xFF, 0x21}, -{0x54, 0xFF, 0x2A}, -{0x55, 0xFF, 0x96}, -{0x52, 0xFF, 0xA2}, -{0x56, 0xFF, 0x81}, -{0x57, 0xFF, 0xC0}, -{0x60, 0xFF, 0xFB}, -{0x61, 0xFF, 0xAA}, -{0x62, 0xFF, 0xFB}, -{0x63, 0xFF, 0xAA}, -{0x81, 0xFF, 0xB3}, -{0x82, 0xFF, 0x72}, -{0x83, 0xFF, 0x40}, -{0x85, 0xFF, 0xB3}, -{0x86, 0xFF, 0x72}, -{0x87, 0xFF, 0x40}, -{0x94, 0xFF, 0xC0}, -{0x95, 0xFF, 0x08}, -{0x96, 0xFF, 0xC0}, -{0x97, 0xFF, 0x08}, -{0x98, 0xFF, 0xCC}, -{0x99, 0xFF, 0x04}, -{0x9A, 0xFF, 0x0C}, -{0x9B, 0xFF, 0x14}, -{0xA0, 0xFF, 0x11}, -{0x57, 0xFF, 0xD0}, - -{0xD8, 0xFE, 0x01}, // Com reset -{0xC8, 0xFE, 0x01}, -{0xC4, 0xFF, 0xFF}, // Clear status -{0xC5, 0xFF, 0xFF}, -{0xC6, 0xFF, 0xFF}, -{0xC7, 0xFF, 0xFF}, -{0xD4, 0xFF, 0xFF}, -{0xD5, 0xFF, 0xFF}, -{0xD6, 0xFF, 0xFF}, -{0xD7, 0xFF, 0xFF}, - - -{0x2C, 0xFF, 0x39}, // set subsystem ID -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x13}, -{0x2F, 0xFF, 0x55}, - - -{0x00, 0x00, 0x00} //End of table -}; - -static void ide_init(struct device *dev) -{ - struct southbridge_sis_sis966_config *conf; - /* Enable ide devices so the linux ide driver will work */ - uint32_t dword; - uint16_t word; - uint8_t byte; - conf = dev->chip_info; - - - -printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); - - -//-------------- enable IDE (SiS5513) ------------------------- -{ - uint8_t temp8; - int i=0; - while (SiS_SiS5513_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); - temp8 &= SiS_SiS5513_init[i][1]; - temp8 |= SiS_SiS5513_init[i][2]; - pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); - i++; - }; -} -//----------------------------------------------------------- - - word = pci_read_config16(dev, 0x50); - /* Ensure prefetch is disabled */ - word &= ~((1 << 15) | (1 << 13)); - if (conf->ide1_enable) { - /* Enable secondary ide interface */ - word |= (1<<0); - printk(BIOS_DEBUG, "IDE1\t"); - } - if (conf->ide0_enable) { - /* Enable primary ide interface */ - word |= (1<<1); - printk(BIOS_DEBUG, "IDE0\n"); - } - - word |= (1<<12); - word |= (1<<14); - - pci_write_config16(dev, 0x50, word); - - - byte = 0x20; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); - - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); - -#if DEBUG_IDE -{ - int i; - - printk(BIOS_DEBUG, "****** IDE PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i=0;i<0xff;i+=4) { - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); -} -#endif -printk(BIOS_DEBUG, "IDE_INIT:<----------\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = sis966_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_IDE, -}; diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c deleted file mode 100644 index 51ee233a7f..0000000000 --- a/src/southbridge/sis/sis966/lpc.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Linux Networx - * Copyright (C) 2003 SuSE Linux AG - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pnp.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include "sis966.h" -#include <pc80/keyboard.h> - -#define NMI_OFF 0 - -// 0x7a or e3 -#define PREVIOUS_POWER_STATE 0x7A - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define SLOW_CPU_OFF 0 -#define SLOW_CPU__ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -#undef SLAVE_INIT - -static void lpc_common_init(struct device *dev) -{ - uint8_t byte; - void *ioapic_base; - - /* IO APIC initialization */ - byte = pci_read_config8(dev, 0x74); - byte |= (1<<0); // enable APIC - pci_write_config8(dev, 0x74, byte); - ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 - - setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID -} - -#ifdef SLAVE_INIT -static void lpc_slave_init(struct device *dev) -{ - lpc_common_init(dev); -} -#endif - -static void lpc_usb_legacy_init(struct device *dev) -{ - uint16_t acpi_base; - - acpi_base = (pci_read_config8(dev,0x75) << 8); - - outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb); - outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba); -} - -static void lpc_init(struct device *dev) -{ - uint8_t byte; - uint8_t byte_old; - int on; - int nmi_option; - - printk(BIOS_DEBUG, "LPC_INIT -------->\n"); - pc_keyboard_init(NO_AUX_DEVICE); - - lpc_usb_legacy_init(dev); - lpc_common_init(dev); - - /* power after power fail */ - - - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; - if (!on) { - byte |= 0x40; - } - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); - - /* Throttle the CPU speed down for testing */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if (on) { - uint16_t pm10_bar; - uint32_t dword; - pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); - outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); - on = 8-on; - printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on*12)+(on>>1),(on&1)*5); - } - - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if ( byte != byte_old) { - outb(byte, 0x70); - } - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - printk(BIOS_DEBUG, "LPC_INIT <--------\n"); -} - -static void sis966_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -/** - * Enable resources for children devices. - * - * @param dev The device whose children's resources are to be enabled. - */ -static void sis966_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - uint32_t reg, reg_var[4]; - int i; - int var_num = 0; - - reg = pci_read_config32(dev, 0xa0); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; child = child->sibling) { - if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long - if (!(res->flags & IORESOURCE_IO)) continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); - switch (base) { - case 0x3f8: // COM1 - reg |= (1<<0); break; - case 0x2f8: // COM2 - reg |= (1<<1); break; - case 0x378: // Parallel 1 - reg |= (1<<24); break; - case 0x3f0: // FD0 - reg |= (1<<20); break; - case 0x220: // Audio 0 - reg |= (1<<8); break; - case 0x300: // Midi 0 - reg |= (1<<12); break; - } - if ( (base == 0x290) || (base >= 0x400)) { - if (var_num>=4) continue; // only 4 var ; compact them ? - reg |= (1<<(28+var_num)); - reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); - } - } - } - } - } - pci_write_config32(dev, 0xa0, reg); - for (i=0;i<var_num;i++) { - pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); - } - - -} - -static void sis966_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - sis966_lpc_enable_childrens_resources(dev); -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations lpc_ops = { - .read_resources = sis966_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = sis966_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_lpc_bus, -// .enable = sis966_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_LPC, -}; - -#ifdef SLAVE_INIT // No device? -static struct device_operations lpc_slave_ops = { - .read_resources = sis966_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_slave_init, -// .enable = sis966_enable, - .ops_pci = &lops_pci, -}; -#endif diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c deleted file mode 100644 index 6c6a08a538..0000000000 --- a/src/southbridge/sis/sis966/nic.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> -#include <delay.h> -#include "sis966.h" - - -u8 SiS_SiS191_init[6][3]={ - {0x04, 0xFF, 0x07}, - {0x2C, 0xFF, 0x39}, - {0x2D, 0xFF, 0x10}, - {0x2E, 0xFF, 0x91}, - {0x2F, 0xFF, 0x01}, - {0x00, 0x00, 0x00} //End of table -}; - - -#define StatusReg 0x1 -#define SMI_READ 0x0 -#define SMI_REQUEST 0x10 -#define TRUE 1 -#define FALSE 0 - -u16 MacAddr[3]; - - -static void writeApcByte(int addr, u8 value) -{ - outb(addr, 0x78); - outb(value, 0x79); -} - -static u8 readApcByte(int addr) -{ - u8 value; - outb(addr, 0x78); - value = inb(0x79); - return(value); -} - -static void readApcMacAddr(void) -{ - u8 i; - -// enable APC in south bridge sis966 D2F0 - - outl(0x80001048, 0xcf8); - outl((inl(0xcfc) & 0xfffffffd), 0xcfc ); // enable IO78/79h for APC Index/Data - - printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9; i <= 0xe; i++) - printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); - - printk(BIOS_DEBUG, "\n"); - - /* Set APC Reload */ - writeApcByte(0x7, readApcByte(0x7) & 0xf7); - writeApcByte(0x7, readApcByte(0x7) | 0x0a); - - /* disable APC in south bridge */ - outl(0x80001048, 0xcf8); - outl(inl(0xcfc) & 0xffffffbf, 0xcfc); -} - -static void set_apc(struct device *dev) -{ - u16 addr; - u16 i; - u8 bTmp; - - /* enable APC in south bridge sis966 D2F0 */ - outl(0x80001048, 0xcf8); - outl((inl(0xcfc) & 0xfffffffd), 0xcfc ); // enable IO78/79h for APC Index/Data - - for (i = 0; i < 3; i++) { - addr = 0x9 + 2*i; - writeApcByte(addr, (u8)(MacAddr[i] & 0xFF)); - writeApcByte(addr+1L, (u8)((MacAddr[i] >> 8) & 0xFF)); - // printf("%x - ", readMacAddrByte(0x59 + i)); - } - - /* Set APC Reload */ - writeApcByte(0x7, readApcByte(0x7) & 0xf7); - writeApcByte(0x7, readApcByte(0x7) | 0x0a); - - /* disable APC in south bridge */ - outl(0x80001048, 0xcf8); - outl(inl(0xcfc) & 0xffffffbf, 0xcfc); - - // CFG reg0x73 bit = 1, tell driver MAC Address load to APC - bTmp = pci_read_config8(dev, 0x73); - bTmp |= 0x1; - pci_write_config8(dev, 0x73, bTmp); -} - -/** - * Read one word out of the serial EEPROM. - * - * @param dev TODO - * @param base TODO - * @param Reg EEPROM word to read. - * @return Contents of EEPROM word (Reg). - */ -#define LoopNum 200 -static unsigned long ReadEEprom(struct device *dev, u8 *base, u32 Reg) -{ - u32 data; - u32 i; - u32 ulValue; - - ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7 - - write32(base + 0x3c, ulValue); - - mdelay(10); - - for (i = 0; i <= LoopNum; i++) { - ulValue = read32(base + 0x3c); - - if (!(ulValue & 0x0080)) //BIT_7 - break; - - mdelay(100); - } - - mdelay(50); - - if (i == LoopNum) - data = 0x10000; - else { - ulValue = read32(base + 0x3c); - data = ((ulValue & 0xffff0000) >> 16); - } - - return data; -} - -static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg) -{ - u32 ulValue; - u32 Read_Cmd; - u16 usData; - - Read_Cmd = ((phy_reg << 11) | - (phy_addr << 6) | - SMI_READ | - SMI_REQUEST); - - // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC - write32(base + 0x44, Read_Cmd); - - // Polling SMI_REQ bit to be deasserted indicated read command completed - do { - // Wait 20 usec before checking status - mdelay(20); - ulValue = read32(base + 0x44); - } while ((ulValue & SMI_REQUEST) != 0); - //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); - usData = (ulValue >> 16); - - return usData; -} - -// Detect a valid PHY -// If there exist a valid PHY then return TRUE, else return FALSE -static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() -{ - int bFoundPhy = FALSE; - u16 usData; - int PhyAddress = 0; - - - // Scan all PHY address(0 ~ 31) to find a valid PHY - for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) { - // Status register is a PHY's register(offset 01h) - usData = phy_read(base,PhyAddress,StatusReg); - - // Found a valid PHY - if ((usData != 0x0) && (usData != 0xffff)) { - bFoundPhy = TRUE; - break; - } - } - - if (!bFoundPhy) - printk(BIOS_DEBUG, "PHY not found !!!!\n"); - - *PhyAddr = PhyAddress; - - return bFoundPhy; -} - - -static void nic_init(struct device *dev) -{ - int val; - u16 PhyAddr; - u8 *base; - struct resource *res; - - printk(BIOS_DEBUG, "NIC_INIT:---------->\n"); - -//-------------- enable NIC (SiS19x) ------------------------- -{ - u8 temp8; - int i = 0; - while (SiS_SiS191_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); - temp8 &= SiS_SiS191_init[i][1]; - temp8 |= SiS_SiS191_init[i][2]; - pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); - i++; - }; -} -//----------------------------------------------------------- - -{ - unsigned long i; - unsigned long ulValue; - - res = find_resource(dev, 0x10); - - if (!res) { - printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); - return; - } - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "NIC base address %p\n",base); - - if (!(val = phy_detect(base, &PhyAddr))) { - printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); - return; - } - - ulValue = read32(base + 0x38L); // check EEPROM existing - - if (ulValue & 0x0002) { - - // read MAC address from EEPROM at first - - // if that is valid we will use that - - printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom(dev, base, 0LL)); - for (i = 0; i < 3; i++) { - //status = smbus_read_byte(dev_eeprom, i); - ulValue = ReadEEprom(dev, base, i + 3L); - if (ulValue == 0x10000) - break; // error - - MacAddr[i] = ulValue & 0xFFFF; - - } - } else { - // read MAC address from firmware - printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue); - MacAddr[0] = read16((u16 *)0xffffffc0); // mac address store at here - MacAddr[1] = read16((u16 *)0xffffffc2); - MacAddr[2] = read16((u16 *)0xffffffc4); - } - - set_apc(dev); - - readApcMacAddr(); - -#if DEBUG_NIC -{ - int i; - - printk(BIOS_DEBUG, "****** NIC PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i = 0; i < 0xff; i += 4) { - if ((i%16) == 0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev, i)); - } - printk(BIOS_DEBUG, "\n"); -} - -#endif - -} - -printk(BIOS_DEBUG, "NIC_INIT:<----------\n"); -return; - -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -// .enable = sis966_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_NIC, -}; diff --git a/src/southbridge/sis/sis966/pcie.c b/src/southbridge/sis/sis966/pcie.c deleted file mode 100644 index e27960e0fc..0000000000 --- a/src/southbridge/sis/sis966/pcie.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "sis966.h" - -static void pcie_init(struct device *dev) -{ - - /* Enable pci error detecting */ - uint32_t dword; - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* System error enable */ - dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); - -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, -// .enable = sis966_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pciebc_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_PCIE, -}; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c deleted file mode 100644 index 7be98d7a2f..0000000000 --- a/src/southbridge/sis/sis966/reset.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <reset.h> - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void do_hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); -} diff --git a/src/southbridge/sis/sis966/romstrap.S b/src/southbridge/sis/sis966/romstrap.S deleted file mode 100644 index 1eb39e3e6a..0000000000 --- a/src/southbridge/sis/sis966/romstrap.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x56341200 // 30h, MAC address low 4 byte ---> keep it in 0xffffffc0 - .long 0x00009078 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - - .long 0x00402000 //Firmware trap for SiS761+966 - .long 0xE043A800 - .long 0x00180000 - .long 0x1421C402 - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/sis/sis966/romstrap.ld b/src/southbridge/sis/sis966/romstrap.ld deleted file mode 100644 index 621cebd9e2..0000000000 --- a/src/southbridge/sis/sis966/romstrap.ld +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - KEEP(*(.romstrap)) - } -} diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c deleted file mode 100644 index 68994d4ff7..0000000000 --- a/src/southbridge/sis/sis966/sata.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <delay.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "sis966.h" -#include <arch/io.h> - -uint8_t SiS_SiS1183_init[68][3] = { - {0x04, 0x00, 0x05}, - {0x09, 0x00, 0x05}, - {0x2C, 0x00, 0x39}, - {0x2D, 0x00, 0x10}, - {0x2E, 0x00, 0x83}, - {0x2F, 0x00, 0x11}, - {0x90, 0x00, 0x40}, - {0x91, 0x00, 0x00}, // set mode - {0x50, 0x00, 0xA2}, - {0x52, 0x00, 0xA2}, - {0x55, 0x00, 0x96}, - {0x52, 0x00, 0xA2}, - {0x55, 0xF7, 0x00}, - {0x56, 0x00, 0xC0}, - {0x57, 0x00, 0x14}, - {0x67, 0x00, 0x28}, - {0x81, 0x00, 0xB3}, - {0x82, 0x00, 0x72}, - {0x83, 0x00, 0x40}, - {0x85, 0x00, 0xB3}, - {0x86, 0x00, 0x72}, - {0x87, 0x00, 0x40}, - {0x88, 0x00, 0xDE}, // after set mode - {0x89, 0x00, 0xB3}, - {0x8A, 0x00, 0x72}, - {0x8B, 0x00, 0x40}, - {0x8C, 0x00, 0xDE}, - {0x8D, 0x00, 0xB3}, - {0x8E, 0x00, 0x92}, - {0x8F, 0x00, 0x40}, - {0x93, 0x00, 0x00}, - {0x94, 0x00, 0x80}, - {0x95, 0x00, 0x08}, - {0x96, 0x00, 0x80}, - {0x97, 0x00, 0x08}, - {0x9C, 0x00, 0x80}, - {0x9D, 0x00, 0x08}, - {0x9E, 0x00, 0x80}, - {0x9F, 0x00, 0x08}, - {0xA0, 0x00, 0x15}, - {0xA1, 0x00, 0x15}, - {0xA2, 0x00, 0x15}, - {0xA3, 0x00, 0x15}, - - {0xD8, 0xFE, 0x01}, // Com reset - {0xC8, 0xFE, 0x01}, - {0xE8, 0xFE, 0x01}, - {0xF8, 0xFE, 0x01}, - - {0xD8, 0xFE, 0x00}, // Com reset - {0xC8, 0xFE, 0x00}, - {0xE8, 0xFE, 0x00}, - {0xF8, 0xFE, 0x00}, - - {0xC4, 0xFF, 0xFF}, // Clear status - {0xC5, 0xFF, 0xFF}, - {0xC6, 0xFF, 0xFF}, - {0xC7, 0xFF, 0xFF}, - {0xD4, 0xFF, 0xFF}, - {0xD5, 0xFF, 0xFF}, - {0xD6, 0xFF, 0xFF}, - {0xD7, 0xFF, 0xFF}, - {0xE4, 0xFF, 0xFF}, // Clear status - {0xE5, 0xFF, 0xFF}, - {0xE6, 0xFF, 0xFF}, - {0xE7, 0xFF, 0xFF}, - {0xF4, 0xFF, 0xFF}, - {0xF5, 0xFF, 0xFF}, - {0xF6, 0xFF, 0xFF}, - {0xF7, 0xFF, 0xFF}, - - {0x00, 0x00, 0x00} // End of table -}; - -static void sata_init(struct device *dev) -{ - struct southbridge_sis_sis966_config *conf; - int i; - uint32_t temp32; - uint8_t temp8; - - conf = dev->chip_info; - printk(BIOS_DEBUG, "SATA_INIT:---------->\n"); - - /* Enable IDE (SiS1183) */ - i = 0; - while (SiS_SiS1183_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; - }; - - for (i = 0; i < 10; i++) { - temp32 = pci_read_config32(dev, 0xC0); - printk(BIOS_DEBUG, "status= %x\n", temp32); - if (((temp32 & 0xF) == 0x3) || ((temp32 & 0xF) == 0x0)) - break; - } - -#if DEBUG_SATA - printk(BIOS_DEBUG, "****** SATA PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i = 0; i < 0xff; i += 4) { - if ((i % 16) == 0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev, i)); - } - printk(BIOS_DEBUG, "\n"); -#endif - - printk(BIOS_DEBUG, "SATA_INIT:<----------\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -// .enable = sis966_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_SATA, -}; diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c deleted file mode 100644 index 93f8142b4f..0000000000 --- a/src/southbridge/sis/sis966/sis761.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Turn off machine check triggers when reading - * pci space where there are no devices. - * This is necessary when scanning the bus for - * devices which is done by the kernel - * - * written in 2003 by Eric Biederman - * - * - Athlon64 workarounds by Stefan Reinauer - * - "reset once" logic by Yinghai Lu - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <cpu/amd/model_fxx_rev.h> -#include <arch/io.h> - -typedef struct msr_struct -{ - unsigned lo; - unsigned hi; -} msr_t; - -static inline msr_t rdmsr(unsigned index) -{ - msr_t result; - result.lo = 0; - result.hi = 0; - return result; -} - -/** - * Read resources for AGP aperture. - * - * There is only one AGP aperture resource needed. The resource is added to - * the northbridge of BSP. - * - * The same trick can be used to augment legacy VGA resources which can - * be detect by generic PCI resource allocator for VGA devices. - * BAD: it is more tricky than I think, the resource allocation code is - * implemented in a way to NOT DOING legacy VGA resource allocation on - * purpose :-(. - * - * @param dev TODO - */ -static void sis761_read_resources(struct device *dev) -{ - /* Read the generic PCI resources */ - printk(BIOS_DEBUG, "sis761_read_resources ------->\n"); - pci_dev_read_resources(dev); - - /* If we are not the first processor don't allocate the gart aperture */ - if (dev->path.pci.devfn != PCI_DEVFN(0x0, 0)) { - printk(BIOS_DEBUG, "sis761_not_the_first_processor !!!\n"); - return; - } - - printk(BIOS_DEBUG, "sis761_read_resources <-------\n"); - return; - -} - -static void sis761_set_resources(struct device *dev) -{ - printk(BIOS_DEBUG, "sis761_set_resources ------->\n"); - - /* Set the generic PCI resources */ - pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "sis761_set_resources <-------\n"); -} - -static void sis761_init(struct device *dev) -{ - int needs_reset; - msr_t msr; - - - needs_reset = 0; - printk(BIOS_DEBUG, "sis761_init: ---------->\n"); - - msr = rdmsr(0xC001001A); - pci_write_config16(dev, 0x8E, msr.lo >> 16); // Topbound - pci_write_config8(dev, 0x7F, 0x08); // ACPI Base - outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function - - printk(BIOS_DEBUG, "sis761_init: <----------\n"); -} - - -static struct device_operations sis761_ops = { - .read_resources = sis761_read_resources, - .set_resources = sis761_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sis761_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver sis761_driver __pci_driver = { - .ops = &sis761_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS761, -}; diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c deleted file mode 100644 index 3b1b564816..0000000000 --- a/src/southbridge/sis/sis966/sis966.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> - -#include <arch/io.h> - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "sis966.h" - -static uint32_t final_reg; - -static struct device *find_lpc_dev( struct device *dev, unsigned devfn) -{ - - struct device *lpc_dev; - - lpc_dev = dev_find_slot(dev->bus->secondary, devfn); - - if ( !lpc_dev ) return lpc_dev; - -if ((lpc_dev->vendor != PCI_VENDOR_ID_SIS) || ( - (lpc_dev->device != PCI_DEVICE_ID_SIS_SIS966_LPC) - ) ) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16))) - ) { - lpc_dev = 0; - } - } - - return lpc_dev; -} - -void sis966_enable(struct device *dev) -{ - struct device *lpc_dev = NULL; - struct device *sm_dev = NULL; - uint16_t index = 0; - uint16_t index2 = 0; - uint32_t reg_old, reg; - uint8_t byte; - uint16_t deviceid; - uint16_t vendorid; - uint16_t devfn; - - struct southbridge_sis_sis966_config *conf; - conf = dev->chip_info; - int i; - - if (dev->device == 0x0000) { - reg = pci_read_config32(dev, PCI_VENDOR_ID); - deviceid = (reg >> 16) & 0xffff; - vendorid = reg & 0xffff; - } else { -// vendorid = dev->vendor; - deviceid = dev->device; - } - - devfn = (dev->path.pci.devfn) & ~7; - switch (deviceid) { - case PCI_DEVICE_ID_SIS_SIS966_USB: - devfn -= (1<<3); - index = 8; - break; - case PCI_DEVICE_ID_SIS_SIS966_USB2: - devfn -= (1<<3); - index = 20; - break; - case PCI_DEVICE_ID_SIS_SIS966_NIC: - devfn -= (7<<3); - index = 10; - for (i=0;i<2;i++) { - lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); - if (!lpc_dev) continue; - index -= i; - devfn -= (i<<3); - break; - } - break; - case PCI_DEVICE_ID_SIS_SIS966_HD_AUDIO: - devfn -= (5<<3); - index = 11; - break; - case PCI_DEVICE_ID_SIS_SIS966_IDE: - devfn -= (3<<3); - index = 14; - break; - case PCI_DEVICE_ID_SIS_SIS966_SATA: - devfn -= (4<<3); - index = 22; - i = (dev->path.pci.devfn) & 7; - if (i>0) { - index -= (i+3); - } - break; - case PCI_DEVICE_ID_SIS_SIS966_PCIE: - devfn -= (0x9<<3); // to LPC - index2 = 9; - break; - default: - index = 0; - } - - if (!lpc_dev) - lpc_dev = find_lpc_dev(dev, devfn); - - if ( !lpc_dev ) return; - - if (index2!=0) { - sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if (!sm_dev) return; - - if ( sm_dev ) { - reg_old = reg = pci_read_config32(sm_dev, 0xe4); - - if (!dev->enabled) { //disable it - reg |= (1<<index2); - } - - if (reg != reg_old) { - pci_write_config32(sm_dev, 0xe4, reg); - } - } - - index2 = 0; - return; - } - - - if ( index == 0) { // for LPC - - // expose ioapic base - byte = pci_read_config8(lpc_dev, 0x74); - byte |= ((1<<1)); // expose the BAR - pci_write_config8(dev, 0x74, byte); - - // expose trap base - byte = pci_read_config8(lpc_dev, 0xdd); - byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write - pci_write_config8(dev, 0xdd, byte); - return; - - } - - if ( index == 16) { - sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if (!sm_dev) return; - - final_reg = pci_read_config32(sm_dev, 0xe8); - final_reg &= ~0x0057cf00; - pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first - } - - if (!dev->enabled) { - final_reg |= (1 << index);// disable it - /* - * The reason for using final_reg is that if func 1 is disabled, - * then func 2 will become func 1. - * Because of this, we need loop through disabling them all at - * the same time. - */ - } - - if (index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 - sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if (!sm_dev) return; - reg_old = pci_read_config32(sm_dev, 0xe8); - if (final_reg != reg_old) { - pci_write_config32(sm_dev, 0xe8, final_reg); - } - - } -} - -struct chip_operations southbridge_sis_sis966_ops = { - CHIP_NAME("SiS SiS966 Southbridge") - .enable_dev = sis966_enable, -}; diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h deleted file mode 100644 index bc59546aa3..0000000000 --- a/src/southbridge/sis/sis966/sis966.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SIS966_H -#define SIS966_H - -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE -#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - -#define DEBUG_AZA 0 -#define DEBUG_NIC 0 -#define DEBUG_IDE 0 -#define DEBUG_SATA 0 -#define DEBUG_USB 0 -#define DEBUG_USB2 0 - -#ifndef __SIMPLE_DEVICE__ -void sis966_enable(struct device *dev); -#endif - -#endif /* SIS966_H */ diff --git a/src/southbridge/sis/sis966/smbus.h b/src/southbridge/sis/sis966/smbus.h deleted file mode 100644 index a96a9c2044..0000000000 --- a/src/southbridge/sis/sis966/smbus.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/smbus_def.h> - -#define SMBHSTSTAT 0x1 -#define SMBHSTPRTCL 0x0 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x2 -#define SMBHSTDAT0 0x4 -#define SMBHSTDAT1 0x5 - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100*1000*10) - -int smbus_wait_until_ready(unsigned smbus_io_base); -int smbus_wait_until_done(unsigned smbus_io_base); -int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device); -int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val); -int smbus_read_byte(unsigned device, unsigned address); -int smbus_write_byte(unsigned device, unsigned address, unsigned char val); diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c deleted file mode 100644 index fce6002198..0000000000 --- a/src/southbridge/sis/sis966/usb.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "sis966.h" - -uint8_t SiS_SiS7001_init[16][3]={ -{0x04, 0x00, 0x07}, -{0x0C, 0x00, 0x08}, -{0x0D, 0x00, 0x20}, - -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x01}, -{0x2F, 0xFF, 0x70}, - -{0x44, 0x00, 0x54}, -{0x45, 0x00, 0xAD}, -{0x46, 0x00, 0x01}, -{0x47, 0x00, 0x00}, - -{0x48, 0x00, 0x73}, -{0x49, 0x00, 0x02}, -{0x4A, 0x00, 0x00}, -{0x4B, 0x00, 0x00}, - -{0x00, 0x00, 0x00} //End of table -}; - -static void usb_init(struct device *dev) -{ - printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n"); - -//-------------- enable USB1.1 (SiS7001) ------------------------- -{ - uint8_t temp8; - int i=0; - - while (SiS_SiS7001_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); - temp8 &= SiS_SiS7001_init[i][1]; - temp8 |= SiS_SiS7001_init[i][2]; - pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8); - i++; - }; -} -//----------------------------------------------------------- - -#if DEBUG_USB -{ - int i; - - printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i=0;i<0xff;i+=4) { - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); -} -#endif - printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, -// .enable = sis966_enable, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_USB, -}; diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c deleted file mode 100644 index d99b694d4f..0000000000 --- a/src/southbridge/sis/sis966/usb2.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. - * Copyright (C) 2006,2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> -#include "sis966.h" -#include <device/pci_ehci.h> - -static const u8 SiS_SiS7002_init[22][3]={ - {0x04, 0x00, 0x06}, - {0x0D, 0x00, 0x00}, - - {0x2C, 0xFF, 0x39}, - {0x2D, 0xFF, 0x10}, - {0x2E, 0xFF, 0x02}, - {0x2F, 0xFF, 0x70}, - - {0x74, 0x00, 0x00}, - {0x75, 0x00, 0x00}, - {0x76, 0x00, 0x00}, - {0x77, 0x00, 0x00}, - - {0x7A, 0x00, 0x00}, - {0x7B, 0x00, 0x00}, - - {0x40, 0x00, 0x20}, - {0x41, 0x00, 0x00}, - {0x42, 0x00, 0x00}, - {0x43, 0x00, 0x08}, - - {0x44, 0x00, 0x04}, - - {0x48, 0x00, 0x10}, - {0x49, 0x00, 0x80}, - {0x4A, 0x00, 0x07}, - {0x4B, 0x00, 0x00}, - - {0x00, 0x00, 0x00} //End of table -}; - -static void usb2_init(struct device *dev) -{ - u8 *base; - struct resource *res; - int i; - u8 temp8; - - printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n"); - - //-------------- enable USB2.0 (SiS7002) ---------------------- - - i = 0; - while (SiS_SiS7002_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); - temp8 &= SiS_SiS7002_init[i][1]; - temp8 |= SiS_SiS7002_init[i][2]; - pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); - i++; - }; - - res = find_resource(dev, 0x10); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "base = 0x%p\n", base); - write32(base + 0x20, 0x2); - //------------------------------------------------------------- - -#if DEBUG_USB2 - printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i=0;i<0xff;i+=4) { - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); -#endif - printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations usb2_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb2_init, -// .enable = sis966_enable, - .scan_bus = 0, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_USB2, -}; |