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Diffstat (limited to 'src/southbridge/nvidia')
-rw-r--r--src/southbridge/nvidia/ck804/ck804_nic.c10
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_aza.c26
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_nic.c28
3 files changed, 32 insertions, 32 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/ck804_nic.c
index 4ad0d11a62..cb8015c16b 100644
--- a/src/southbridge/nvidia/ck804/ck804_nic.c
+++ b/src/southbridge/nvidia/ck804/ck804_nic.c
@@ -27,7 +27,7 @@ static void nic_init(struct device *dev)
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
- writel(PHY_RGMII, base + NvRegPhyInterface);
+ write32(base + NvRegPhyInterface, PHY_RGMII);
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
@@ -76,15 +76,15 @@ static void nic_init(struct device *dev)
if (!eeprom_valid) {
unsigned long mac_pos;
mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
- mac_l = readl((uint8_t*)mac_pos) + nic_index;
- mac_h = readl((uint8_t*)mac_pos + 4);
+ mac_l = read32((uint8_t*)mac_pos) + nic_index;
+ mac_h = read32((uint8_t*)mac_pos + 4);
}
#if 1
/* Set that into NIC MMIO. */
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
- writel(mac_l, base + NvRegMacAddrA);
- writel(mac_h, base + NvRegMacAddrB);
+ write32(base + NvRegMacAddrA, mac_l);
+ write32(base + NvRegMacAddrB, mac_h);
#else
/* Set that into NIC. */
pci_write_config32(dev, 0xa8, mac_l);
diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c
index b43c8fd281..b86530b7af 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_aza.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_aza.c
@@ -36,14 +36,14 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val)
int count;
val &= mask;
- dword = readl(port);
+ dword = read32(port);
dword &= ~mask;
dword |= val;
- writel(dword, port);
+ write32(port, dword);
count = 50;
do {
- dword = readl(port);
+ dword = read32(port);
dword &= mask;
udelay(100);
} while ((dword != val) && --count);
@@ -63,9 +63,9 @@ static int codec_detect(uint8_t *base)
set_bits(base + 0x08, 1, 1);
/* 2 */
- dword = readl(base + 0x0e);
+ dword = read32(base + 0x0e);
dword |= 7;
- writel(dword, base + 0x0e);
+ write32(base + 0x0e, dword);
/* 3 */
set_bits(base + 0x08, 1, 0);
@@ -74,7 +74,7 @@ static int codec_detect(uint8_t *base)
set_bits(base + 0x08, 1, 1);
/* 5 */
- dword = readl(base + 0xe);
+ dword = read32(base + 0xe);
dword &= 7;
/* 6 */
@@ -173,17 +173,17 @@ static void codec_init(uint8_t *base, int addr)
/* 1 */
do {
- dword = readl(base + 0x68);
+ dword = read32(base + 0x68);
} while (dword & 1);
dword = (addr<<28) | 0x000f0000;
- writel(dword, base + 0x60);
+ write32(base + 0x60, dword);
do {
- dword = readl(base + 0x68);
+ dword = read32(base + 0x68);
} while ((dword & 3)!=2);
- dword = readl(base + 0x64);
+ dword = read32(base + 0x64);
/* 2 */
printk_debug("codec viddid: %08x\n", dword);
@@ -198,13 +198,13 @@ static void codec_init(uint8_t *base, int addr)
/* 3 */
for(i=0; i<verb_size; i++) {
do {
- dword = readl(base + 0x68);
+ dword = read32(base + 0x68);
} while (dword & 1);
- writel(verb[i], base + 0x60);
+ write32(base + 0x60, verb[i]);
do {
- dword = readl(base + 0x68);
+ dword = read32(base + 0x68);
} while ((dword & 3) != 2);
}
printk_debug("verb loaded!\n");
diff --git a/src/southbridge/nvidia/mcp55/mcp55_nic.c b/src/southbridge/nvidia/mcp55/mcp55_nic.c
index 839c05bf46..d3b92b97bb 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_nic.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_nic.c
@@ -35,22 +35,22 @@ static int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg)
{
uint32_t dword;
unsigned loop = 0x100;
- writel(0x8000, base+0x190); //Clear MDIO lock bit
+ write32(base+0x190, 0x8000); //Clear MDIO lock bit
mdelay(1);
- dword = readl(base+0x190);
+ dword = read32(base+0x190);
if(dword & (1<<15)) return -1;
- writel(1, base+0x180);
- writel((phy_addr<<5) | (phy_reg),base + 0x190);
+ write32(base+0x180, 1);
+ write32(base + 0x190, (phy_addr<<5) | (phy_reg));
do{
- dword = readl(base + 0x190);
+ dword = read32(base + 0x190);
if(--loop==0) return -4;
} while ((dword & (1<<15)) );
- dword = readl(base + 0x180);
+ dword = read32(base + 0x180);
if(dword & 1) return -3;
- dword = readl(base + 0x194);
+ dword = read32(base + 0x194);
return dword;
@@ -62,9 +62,9 @@ static void phy_detect(uint8_t *base)
int i;
int val;
unsigned id;
- dword = readl(base+0x188);
+ dword = read32(base+0x188);
dword &= ~(1<<20);
- writel(dword, base+0x188);
+ write32(base+0x188, dword);
phy_read(base, 0, 1);
@@ -116,7 +116,7 @@ static void nic_init(struct device *dev)
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
- writel(PHY_RGMII, base + NvRegPhyInterface);
+ write32(base + NvRegPhyInterface, PHY_RGMII);
conf = dev->chip_info;
@@ -157,16 +157,16 @@ static void nic_init(struct device *dev)
if(!eeprom_valid) {
unsigned long mac_pos;
mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
- mac_l = readl(mac_pos) + nic_index; // overflow?
- mac_h = readl(mac_pos + 4);
+ mac_l = read32(mac_pos) + nic_index; // overflow?
+ mac_h = read32(mac_pos + 4);
}
#if 1
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
- writel(mac_l, base + NvRegMacAddrA);
- writel(mac_h, base + NvRegMacAddrB);
+ write32(base + NvRegMacAddrA, mac_l);
+ write32(base + NvRegMacAddrB, mac_h);
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 04:21:57 +0000