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-rw-r--r--src/southbridge/nvidia/ck804/lpc.c2
-rw-r--r--src/southbridge/nvidia/ck804/nic.c10
-rw-r--r--src/southbridge/nvidia/mcp55/azalia.c19
-rw-r--r--src/southbridge/nvidia/mcp55/lpc.c4
-rw-r--r--src/southbridge/nvidia/mcp55/nic.c15
5 files changed, 26 insertions, 24 deletions
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 105f5cbb61..37baf994bc 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -65,7 +65,7 @@ static void lpc_common_init(device_t dev)
/* I/O APIC initialization. */
res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */
ASSERT(res != NULL);
- setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
+ setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */
#if 1
dword = pci_read_config32(dev, 0xe4);
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index e285644bec..974ce0d4de 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -33,11 +33,11 @@ static void nic_init(struct device *dev)
int eeprom_valid = 0;
struct southbridge_nvidia_ck804_config *conf;
static u32 nic_index = 0;
- unsigned long base;
+ u8 *base;
struct resource *res;
res = find_resource(dev, 0x10);
- base = (unsigned long)res->base;
+ base = res2mmio(res, 0, 0);
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
@@ -89,10 +89,10 @@ static void nic_init(struct device *dev)
/* If that is invalid we will read that from romstrap. */
if (!eeprom_valid) {
- unsigned long mac_pos;
- mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
+ u32 *mac_pos;
+ mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */
mac_l = read32(mac_pos) + nic_index;
- mac_h = read32(mac_pos + 4);
+ mac_h = read32(mac_pos + 1);
}
#if 1
/* Set that into NIC MMIO. */
diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 67433d310d..490cfa74f9 100644
--- a/src/southbridge/nvidia/mcp55/azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
@@ -31,7 +31,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -58,7 +58,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u8 *base)
{
u32 reg32;
@@ -111,7 +111,7 @@ static u32 find_verb(struct device *dev, u32 viddid, u32 **verb)
* Wait 50usec for the codec to indicate it is ready.
* No response would imply that the codec is non-operative.
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
@@ -130,7 +130,7 @@ static int wait_for_ready(u32 base)
* Wait 50usec for the codec to indicate that it accepted the previous command.
* No response would imply that the code is non-operative.
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u8 *base)
{
u32 reg32;
@@ -152,7 +152,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u8 *base, int addr)
{
u32 reg32, verb_size;
u32 *verb;
@@ -195,7 +195,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -206,7 +206,8 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base, codec_mask, reg32;
+ u8 *base;
+ u32 codec_mask, reg32;
struct resource *res;
u8 reg8;
@@ -244,8 +245,8 @@ static void azalia_init(struct device *dev)
* NOTE: This will break as soon as the Azalia gets a BAR above
* 4G. Is there anything we can do about it?
*/
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 11c2c4f612..5f190b854a 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -60,13 +60,13 @@
static void lpc_common_init(device_t dev, int master)
{
u8 byte;
- u32 ioapic_base;
+ void *ioapic_base;
/* IOAPIC initialization. */
byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable IOAPIC. */
pci_write_config8(dev, 0x74, byte);
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
+ ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
if (master)
setup_ioapic(ioapic_base, 0);
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index fd736e6a0c..136d060d0b 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -31,7 +31,7 @@
#include <delay.h>
#include "mcp55.h"
-static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
{
u32 dword;
unsigned loop = 0x100;
@@ -59,7 +59,7 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
return dword;
}
-static void phy_detect(u32 base)
+static void phy_detect(u8 *base)
{
u32 dword;
int i, val;
@@ -103,7 +103,8 @@ static void phy_detect(u32 base)
static void nic_init(struct device *dev)
{
- u32 mac_h = 0, mac_l = 0, base;
+ u8 *base;
+ u32 mac_h = 0, mac_l = 0;
int eeprom_valid = 0;
struct southbridge_nvidia_mcp55_config *conf;
static u32 nic_index = 0;
@@ -114,7 +115,7 @@ static void nic_init(struct device *dev)
if (!res)
return;
- base = res->base;
+ base = res2mmio(res, 0, 0);
phy_detect(base);
@@ -160,10 +161,10 @@ static void nic_init(struct device *dev)
}
// if that is invalid we will read that from romstrap
if(!eeprom_valid) {
- unsigned long mac_pos;
- mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
+ u32 *mac_pos;
+ mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds
mac_l = read32(mac_pos) + nic_index; // overflow?
- mac_h = read32(mac_pos + 4);
+ mac_h = read32(mac_pos + 1);
}
#if 1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 23:03:15 +0000