diff options
Diffstat (limited to 'src/southbridge/nvidia')
-rw-r--r-- | src/southbridge/nvidia/mcp55/Kconfig | 5 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/bootblock.c | 26 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/chip.h | 2 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55.h | 12 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_enable_rom.c | 9 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c | 6 |
6 files changed, 47 insertions, 13 deletions
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 78a1f254c5..af6bb2bbfc 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,9 +2,14 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool select HAVE_USBDEBUG select IOAPIC + select TINY_BOOTBLOCK if SOUTHBRIDGE_NVIDIA_MCP55 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/nvidia/mcp55/bootblock.c" + config ID_SECTION_OFFSET hex default 0x80 diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c new file mode 100644 index 0000000000..e735b4702c --- /dev/null +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" + +static void bootblock_southbridge_init(void) +{ + mcp55_enable_rom(); +} diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h index a776eb2d09..62a6f7a073 100644 --- a/src/southbridge/nvidia/mcp55/chip.h +++ b/src/southbridge/nvidia/mcp55/chip.h @@ -22,6 +22,8 @@ #ifndef MCP55_CHIP_H #define MCP55_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_mcp55_config { unsigned int ide0_enable : 1; diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index e746cb6398..6199965aa9 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -22,13 +22,21 @@ #ifndef MCP55_H #define MCP55_H -#include "chip.h" +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif #ifndef __PRE_RAM__ +#include "chip.h" void mcp55_enable(device_t dev); extern struct pci_operations mcp55_pci_ops; #else +#if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif void mcp55_enable_usbdebug(unsigned int port); +#endif +#endif + #endif /* MCP55_H */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c index 78e587e063..d08b1d486b 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c @@ -21,11 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "mcp55.h" static void mcp55_enable_rom(void) { diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c index e0b293c81a..2e78fa1ff6 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c @@ -28,12 +28,6 @@ #include <device/pci_def.h> #include "mcp55.h" -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - void set_debug_port(unsigned int port) { u32 dword; |