diff options
Diffstat (limited to 'src/southbridge/nvidia/mcp55')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/enable_usbdebug.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index f629c505c3..b0afec28a4 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -30,10 +30,14 @@ #include <device/pci_def.h> #include "mcp55.h" -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -42,12 +46,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |