diff options
Diffstat (limited to 'src/southbridge/nvidia/ck804')
| -rw-r--r-- | src/southbridge/nvidia/ck804/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_early_smbus.c | 47 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_early_smbus.h | 5 |
3 files changed, 43 insertions, 10 deletions
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 48f7713a8b..09b20708af 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -16,6 +16,7 @@ ramstage-y += ck804_reset.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c romstage-y += ck804_enable_usbdebug.c +romstage-y += ck804_early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c index 6f88c327b0..05dcd98014 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c +++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.c @@ -18,36 +18,63 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + #include "ck804_smbus.h" +#include "ck804_early_smbus.h" +#define SMBUS_BAR_BASE 0x20 #define SMBUS_IO_BASE 0x1000 +#define SMBUS_IO_SIZE 0x0040 + +#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x)) +#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x)) -static void enable_smbus(void) +void enable_smbus(void) { device_t dev; - dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); if (dev == PCI_DEV_INVALID) die("SMBus controller not found\n"); - print_debug("SMBus controller enabled\n"); - /* Set SMBus I/O base. */ - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1); + pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1); /* Set SMBus I/O space enable. */ pci_write_config16(dev, 0x4, 0x01); /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); + outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT); + + print_debug("SMBus controller enabled\n"); } -static int smbus_read_byte(unsigned device, unsigned address) +int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_BASE(bus), device, address); } -static inline int smbus_write_byte(unsigned device, unsigned address, +int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, unsigned char val) { - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); + return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); +} + +int smbus_read_byte(unsigned device, unsigned address) +{ + return ck804_smbus_read_byte(0, device, address); +} + +int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + return ck804_smbus_write_byte(0, device, address, val); } diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.h b/src/southbridge/nvidia/ck804/ck804_early_smbus.h new file mode 100644 index 0000000000..cf25403fdd --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.h @@ -0,0 +1,5 @@ +int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); +int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); +void enable_smbus(void); +int smbus_read_byte(unsigned int, unsigned int); +int smbus_write_byte(unsigned int, unsigned int, unsigned char); |