diff options
Diffstat (limited to 'src/southbridge/nvidia/ck804/enable_rom.c')
| -rw-r--r-- | src/southbridge/nvidia/ck804/enable_rom.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/southbridge/nvidia/ck804/enable_rom.c b/src/southbridge/nvidia/ck804/enable_rom.c new file mode 100644 index 0000000000..facf7959eb --- /dev/null +++ b/src/southbridge/nvidia/ck804/enable_rom.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +static void ck804_enable_rom(void) +{ + unsigned char byte; + device_t addr; + + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ + /* Locate the ck804 LPC. */ + addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); + + /* Set the 4MB enable bit. */ + byte = pci_read_config8(addr, 0x88); + byte |= 0x80; + pci_write_config8(addr, 0x88, byte); +} |