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-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c4
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c3
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c4
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c4
-rw-r--r--src/southbridge/intel/i82801gx/sata.c3
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c4
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c4
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c4
-rw-r--r--src/southbridge/intel/ibexpeak/sata.c3
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c4
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c3
11 files changed, 29 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 2efddd89a1..2407d92dc1 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -520,7 +520,9 @@ static void lpc_init(struct device *dev)
report_pch_info(dev);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 63801a213e..484f0f11a2 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -108,7 +108,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* AHCI */
if (sata_mode == 0) {
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 3a71dbcf6b..dec12666fc 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -253,7 +253,9 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
i82801dx_enable_acpi(dev);
/* IO APIC initialization. */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 9b32f6cfd9..0c7678117f 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -347,7 +347,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801gx_enable_ioapic(dev);
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 6efdef76cb..715d670ae2 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -88,7 +88,8 @@ static void sata_init(struct device *dev)
ports = get_ich7_sata_ports();
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
switch (config->sata_mode) {
case SATA_MODE_IDE_LEGACY_COMBINED:
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index a2df123bc9..6fe9bb9470 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -357,7 +357,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801ix_enable_apic(dev);
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index fceeb3f80e..a8b53706c1 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -361,7 +361,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801jx_enable_apic(dev);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 7e99613a28..230d5eb29f 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -439,7 +439,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 357ad5fc99..21371495eb 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -49,7 +49,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (sata_mode == 0) {
/* AHCI */
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f3298b00c9..7082a79d31 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -505,7 +505,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 47e6f9be68..2f903f04fb 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -41,7 +41,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 16:13:35 +0000