diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/bootblock.c | 15 |
3 files changed, 20 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index af346ab4c8..08042984be 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -45,6 +45,7 @@ config INTEL_LYNXPOINT_LP config EHCI_BAR hex + default 0xd8000000 if USE_BROADWELL_MRC default 0xe8000000 config SERIRQ_CONTINUOUS_MODE diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index bba89f4699..5088d8bb2d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -34,10 +34,14 @@ smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c romstage-y += early_usb.c early_me.c me_status.c early_pch.c romstage-y += pmutil.c +romstage-y += iobp.c romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio +romstage-$(CONFIG_USE_BROADWELL_MRC) += early_pch_native.c early_usb_native.c iobp.c thermal.c +subdirs-$(CONFIG_USE_BROADWELL_MRC) += hsio + ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 495871c6d2..5bdebef418 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -52,6 +52,21 @@ void bootblock_early_southbridge_init(void) pch_enable_lpc(); mainboard_config_superio(); + /* Broadwell MRC.bin uses HPET, but does not enable it beforehand */ + if (CONFIG(USE_BROADWELL_MRC)) { + /* Set HPET address and enable it */ + RCBA32_AND_OR(HPTC, ~3, 1 << 7); + + /* + * Reading the register back guarantees that the write is + * done before we use the configured base address below. + */ + (void)RCBA32(HPTC); + + /* Enable HPET to start counter */ + setbits32((void *)0xfed00000 + 0x10, 1 << 0); + } + if (CONFIG(SERIALIO_UART_CONSOLE)) uart_bootblock_init(); } |