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-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c25
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c25
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c26
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c12
4 files changed, 43 insertions, 45 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index a37d298d06..5b8921012e 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -15,7 +15,6 @@
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <cpu/x86/smm.h>
-#include <cbmem.h>
#include <string.h>
#include "chip.h"
#include "pch.h"
@@ -652,23 +651,23 @@ void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
return &gnvs->chromeos;
}
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
+ if (!gnvs)
+ return;
- if (gnvs) {
-
- acpi_create_gnvs(gnvs);
-
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
- gnvs->pcnt = dev_count_cpu();
+ soc_fill_gnvs(gnvs);
+ acpi_create_gnvs(gnvs);
- /* Add it to DSDT. */
- acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
- acpigen_pop_len();
- }
+ acpi_inject_nvsa();
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 3a89fbec58..06481ffb0b 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -16,7 +16,6 @@
#include <cpu/x86/smm.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
-#include <cbmem.h>
#include <string.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/pmbase.h>
@@ -484,23 +483,21 @@ size_t gnvs_size_of_array(void)
return sizeof(struct global_nvs);
}
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
+ if (!gnvs)
+ return;
- if (gnvs) {
-
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
-
- acpi_create_gnvs(gnvs);
-
-
- /* Add it to SSDT. */
- acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
- acpigen_pop_len();
- }
+ soc_fill_gnvs(gnvs);
+ acpi_create_gnvs(gnvs);
+ acpi_inject_nvsa();
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 4f9a996a16..9ef9e2b390 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -16,7 +16,6 @@
#include <acpi/acpi_gnvs.h>
#include <elog.h>
#include <acpi/acpigen.h>
-#include <cbmem.h>
#include <string.h>
#include <cpu/x86/smm.h>
#include "chip.h"
@@ -547,24 +546,23 @@ size_t gnvs_size_of_array(void)
return sizeof(struct global_nvs);
}
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
+ if (!gnvs)
+ return;
- if (gnvs) {
-
- acpi_create_gnvs(gnvs);
+ soc_fill_gnvs(gnvs);
+ acpi_create_gnvs(gnvs);
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
- gnvs->pcnt = dev_count_cpu();
-
-
- /* Add it to SSDT. */
- acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
- acpigen_pop_len();
- }
+ acpi_inject_nvsa();
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 49c7f7ed3c..be39e5e5c2 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -694,18 +694,22 @@ void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
return &gnvs->chromeos;
}
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+}
+
void southbridge_inject_dsdt(const struct device *dev)
{
struct global_nvs *gnvs = acpi_get_gnvs();
if (!gnvs)
return;
+ soc_fill_gnvs(gnvs);
acpi_create_gnvs(gnvs);
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
- gnvs->pcnt = dev_count_cpu();
-
acpi_inject_nvsa();
}