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-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/esb6300/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/early_init.c2
-rw-r--r--src/southbridge/intel/i3100/lpc.c2
-rw-r--r--src/southbridge/intel/i82371eb/isa.c2
-rw-r--r--src/southbridge/intel/i82801ax/lpc.c2
-rw-r--r--src/southbridge/intel/i82801bx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801cx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ex/lpc.c2
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
15 files changed, 15 insertions, 15 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 75b8a6c91e..0e3a4f6466 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 67bcadc961..b5b77efa14 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -297,7 +297,7 @@ static void lpc_init(struct device *dev)
esb6300_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 2fc3ea7e7b..e5d63b66db 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -305,7 +305,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 0697785b21..bd3d12ccb5 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -69,7 +69,7 @@ static void reset_rtc(void)
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
}
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
void rangeley_sb_early_initialization(void)
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 7c79e5879d..ba74f30748 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -375,7 +375,7 @@ static void lpc_init(struct device *dev)
i3100_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 5605106ddf..5261fbafa3 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -64,7 +64,7 @@ static void isa_init(struct device *dev)
u32 reg32;
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/*
* Enable special cycles, needed for soft poweroff.
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 212c95f270..11519c1fb3 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -190,7 +190,7 @@ static void i82801ax_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STA);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 13b15996dc..278d65c3c1 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -205,7 +205,7 @@ static void i82801bx_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index f9c0ece4fe..f6c33b7feb 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -108,7 +108,7 @@ static void i82801cx_rtc_init(struct device *dev)
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index de09b165d6..1b23fad832 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -200,7 +200,7 @@ static void i82801dx_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index fb1586eb12..1823e65cf4 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -308,7 +308,7 @@ static void lpc_init(struct device *dev)
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 80abb78861..10e40be608 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -294,7 +294,7 @@ static void i82801gx_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 8105a4dc16..664088cd22 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -326,7 +326,7 @@ static void i82801ix_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 31bb4e7921..a833a3d83a 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -294,7 +294,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void mobile5_pm_init(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 64b835f870..a2024242c2 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -301,7 +301,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* LynxPoint PCH Power Management init */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 04:58:18 +0000