diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_lpc.c | 26 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 9f80d41aa4..69bbfb2d02 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -20,6 +20,9 @@ #include <arch/io.h> #include <timestamp.h> +#include <console/console.h> +#include <arch/acpi.h> +#include "i82801gx.h" #if CONFIG_COLLECT_TIMESTAMPS tsc_t get_initial_timestamp(void) @@ -31,3 +34,26 @@ tsc_t get_initial_timestamp(void) return base_time; } #endif + +int southbridge_detect_s3_resume(void) +{ + u32 reg32; + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + return 1; + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + + return 0; +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1064dde8a0..ee13b7d99a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -44,6 +44,7 @@ extern void i82801gx_enable(device_t dev); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); +int southbridge_detect_s3_resume(void); #endif #endif |