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-rw-r--r--src/southbridge/intel/bd82x6x/fadt.c10
-rw-r--r--src/southbridge/intel/i82371eb/fadt.c11
-rw-r--r--src/southbridge/intel/i82801dx/fadt.c10
-rw-r--r--src/southbridge/intel/i82801gx/fadt.c10
-rw-r--r--src/southbridge/intel/i82801ix/fadt.c10
-rw-r--r--src/southbridge/intel/i82801jx/fadt.c10
-rw-r--r--src/southbridge/intel/ibexpeak/fadt.c10
-rw-r--r--src/southbridge/intel/lynxpoint/fadt.c10
8 files changed, 0 insertions, 81 deletions
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index 5d76702d2b..a65a310d5d 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -29,15 +29,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
c2_latency = chip->c2_latency;
if (!c2_latency) {
c2_latency = 101; /* c2 unsupported */
@@ -126,11 +123,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 5086992ab0..ee0b62eca1 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -32,9 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = 0;
fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
- fadt->gpe1_blk = 0x0;
- fadt->gpe1_base = 0;
- fadt->gpe1_blk_len = 0;
/* *_len define register width in bytes */
fadt->pm1_evt_len = 4;
@@ -168,12 +165,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
- fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
- fadt->x_gpe1_blk.addrh = 0x0;
-
}
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c
index 4d1a615aca..288268d8d2 100644
--- a/src/southbridge/intel/i82801dx/fadt.c
+++ b/src/southbridge/intel/i82801dx/fadt.c
@@ -37,7 +37,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = 0x0;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x28;
- fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
@@ -45,8 +44,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 85;
fadt->flush_size = 1024;
@@ -119,11 +116,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c
index 3ab491127b..fd4f7817ed 100644
--- a/src/southbridge/intel/i82801gx/fadt.c
+++ b/src/southbridge/intel/i82801gx/fadt.c
@@ -31,7 +31,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->gpe0_blk = pmbase + GPE0_STS;
- fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2; /* Upper word is reserved and
@@ -39,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->flush_size = 0;
@@ -118,11 +115,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c
index 3b657ad126..c5327b234a 100644
--- a/src/southbridge/intel/i82801ix/fadt.c
+++ b/src/southbridge/intel/i82801ix/fadt.c
@@ -27,7 +27,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->gpe0_blk = pmbase + GPE0_STS;
- fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2; /* Upper word is reserved and
@@ -35,8 +34,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 0x39;
fadt->flush_size = 0;
@@ -109,11 +106,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index c00aa74b9f..4d66670b42 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -30,7 +30,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->gpe0_blk = pmbase + GPE0_STS;
- fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2; /* Upper word is reserved and
@@ -38,8 +37,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->flush_size = 0;
@@ -114,11 +111,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index 7efeae3c1f..dd988910ba 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -29,15 +29,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_blk = pmbase + 0x50;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
c2_latency = chip->c2_latency;
if (!c2_latency) {
c2_latency = 101; /* c2 unsupported */
@@ -125,11 +122,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = pmbase + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c
index 74b07adf30..995532c7eb 100644
--- a/src/southbridge/intel/lynxpoint/fadt.c
+++ b/src/southbridge/intel/lynxpoint/fadt.c
@@ -30,7 +30,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;
else
fadt->gpe0_blk = pmbase + GPE0_STS;
- fadt->gpe1_blk = 0;
/*
* Some of the lengths here are doubled. This is because they describe
@@ -46,8 +45,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 2 * 16;
else
fadt->gpe0_blk_len = 2 * 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
@@ -135,11 +132,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.access_size = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-23 02:44:53 +0000