diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_smbus.h | 127 |
1 files changed, 0 insertions, 127 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h index 1c6f26a47d..a189425395 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h +++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h @@ -63,95 +63,6 @@ static int smbus_wait_until_done(unsigned smbus_io_base) return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned global_status_register; - unsigned byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHST_CMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* set the data word...*/ - outw(0, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHST_DAT) & 0xff; - - // Check for any result other than a command completion - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} - -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value) -{ - unsigned global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHST_CMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* set the data word...*/ - outw(value, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return 0; -} - - static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { unsigned status_register; @@ -199,41 +110,3 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned return byte; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR); - outb(address & 0xFF, smbus_io_base + SMBHST_CMD); - /* set up for a byte data write */ /* FIXME */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x2), smbus_io_base + SMBHST_CTL); - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* write the data word...*/ - outw(val, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) { - return SMBUS_ERROR; - } - return 0; -} - |