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-rw-r--r--src/southbridge/intel/i82801ca/cmos_failover.c4
-rw-r--r--src/southbridge/intel/i82801ca/i82801ca_lpc.c6
-rw-r--r--src/southbridge/intel/i82801dbm/cmos_failover.c2
-rw-r--r--src/southbridge/intel/i82801er/cmos_failover.c2
-rw-r--r--src/southbridge/intel/i82801er/i82801er_lpc.c6
-rw-r--r--src/southbridge/intel/i82801gx/Config.lb4
-rw-r--r--src/southbridge/intel/i82801gx/cmos_failover.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_azalia.c4
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_lpc.c6
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_pci.c8
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_pcie.c2
-rw-r--r--src/southbridge/intel/i82801xx/cmos_failover.c2
12 files changed, 24 insertions, 24 deletions
diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801ca/cmos_failover.c
index 8eb11c3f64..bf35764c19 100644
--- a/src/southbridge/intel/i82801ca/cmos_failover.c
+++ b/src/southbridge/intel/i82801ca/cmos_failover.c
@@ -4,7 +4,7 @@
static void check_cmos_failed(void)
{
-#if HAVE_OPTION_TABLE
+#if CONFIG_HAVE_OPTION_TABLE
uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
if( byte & RTC_BATTERY_DEAD) {
@@ -12,7 +12,7 @@ static void check_cmos_failed(void)
// clear reboot_bits
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
- byte |= MAX_REBOOT_CNT << 4;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
#endif
diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
index b249438a1f..69535bc016 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
@@ -15,8 +15,8 @@
#define NMI_OFF 0
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
#define MAINBOARD_POWER_OFF 0
@@ -88,7 +88,7 @@ void i82801ca_rtc_init(struct device *dev)
{
uint32_t dword;
int rtc_failed;
- int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
diff --git a/src/southbridge/intel/i82801dbm/cmos_failover.c b/src/southbridge/intel/i82801dbm/cmos_failover.c
index 9702313f9c..4821fad3d2 100644
--- a/src/southbridge/intel/i82801dbm/cmos_failover.c
+++ b/src/southbridge/intel/i82801dbm/cmos_failover.c
@@ -10,7 +10,7 @@ static void check_cmos_failed(void)
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
- byte |= MAX_REBOOT_CNT << 4;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}
diff --git a/src/southbridge/intel/i82801er/cmos_failover.c b/src/southbridge/intel/i82801er/cmos_failover.c
index 9702313f9c..4821fad3d2 100644
--- a/src/southbridge/intel/i82801er/cmos_failover.c
+++ b/src/southbridge/intel/i82801er/cmos_failover.c
@@ -10,7 +10,7 @@ static void check_cmos_failed(void)
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
- byte |= MAX_REBOOT_CNT << 4;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c
index 02d474e8d5..fa89469693 100644
--- a/src/southbridge/intel/i82801er/i82801er_lpc.c
+++ b/src/southbridge/intel/i82801er/i82801er_lpc.c
@@ -18,8 +18,8 @@
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
#define ALL (0xff << 24)
@@ -283,7 +283,7 @@ static void lpc_init(struct device *dev)
{
uint8_t byte;
uint32_t value;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* IO APIC initialization */
value = pci_read_config32(dev, 0xd0);
diff --git a/src/southbridge/intel/i82801gx/Config.lb b/src/southbridge/intel/i82801gx/Config.lb
index 53186ed293..9ef5f435e8 100644
--- a/src/southbridge/intel/i82801gx/Config.lb
+++ b/src/southbridge/intel/i82801gx/Config.lb
@@ -17,7 +17,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-uses HAVE_SMI_HANDLER
+uses CONFIG_HAVE_SMI_HANDLER
config chip.h
driver i82801gx.o
@@ -36,7 +36,7 @@ driver i82801gx_usb_ehci.o
object i82801gx_reset.o
object i82801gx_watchdog.o
-if HAVE_SMI_HANDLER
+if CONFIG_HAVE_SMI_HANDLER
object i82801gx_smi.o
smmobject i82801gx_smihandler.o
end
diff --git a/src/southbridge/intel/i82801gx/cmos_failover.c b/src/southbridge/intel/i82801gx/cmos_failover.c
index 0765404ceb..9eae0cbae7 100644
--- a/src/southbridge/intel/i82801gx/cmos_failover.c
+++ b/src/southbridge/intel/i82801gx/cmos_failover.c
@@ -31,7 +31,7 @@ static void check_cmos_failed(void)
// clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
- byte |= MAX_REBOOT_CNT << 4;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}
diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
index fba46bae7c..d0f351413c 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c
@@ -283,7 +283,7 @@ static void azalia_init(struct device *dev)
u8 reg8;
u32 reg32;
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
// ESD
reg32 = pci_mmio_read_config32(dev, 0x134);
reg32 &= 0xff00ffff;
@@ -314,7 +314,7 @@ static void azalia_init(struct device *dev)
reg32 |= (0x80 << 0); // VCi map
pci_mmio_write_config32(dev, 0x120, reg32);
#else
-#error ICH7 Azalia required MMCONF_SUPPORT
+#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
#endif
/* Set Bus Master */
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index 241d610bdd..636b975669 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -185,7 +185,7 @@ static void i82801gx_power_options(device_t dev)
u8 reg8;
u16 reg16;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
@@ -296,7 +296,7 @@ static void enable_clock_gating(void)
RCBA32(0x341c) = reg32;
}
-#if HAVE_SMI_HANDLER
+#if CONFIG_HAVE_SMI_HANDLER
static void i82801gx_lock_smm(struct device *dev)
{
void smm_lock(void);
@@ -401,7 +401,7 @@ static void lpc_init(struct device *dev)
setup_i8259();
-#if HAVE_SMI_HANDLER
+#if CONFIG_HAVE_SMI_HANDLER
i82801gx_lock_smm(dev);
#endif
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c
index 2bf228b135..bf252ec37e 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c
@@ -72,11 +72,11 @@ static void ich_pci_dev_enable_resources(struct device *dev)
if (dev->on_mainboard && ops && ops->set_subsystem) {
printk_debug("%s subsystem <- %02x/%02x\n",
dev_path(dev),
- MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
- MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
ops->set_subsystem(dev,
- MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
- MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
}
command = pci_read_config16(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
index 6965b30972..d7655c5ea5 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
@@ -55,7 +55,7 @@ static void pci_init(struct device *dev)
reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
pci_write_config32(dev, 0xe1, reg32);
-#if MMCONF_SUPPORT
+#if CONFIG_MMCONF_SUPPORT
/* Set VC0 transaction class */
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801xx/cmos_failover.c
index 2ff632548b..9307f40305 100644
--- a/src/southbridge/intel/i82801xx/cmos_failover.c
+++ b/src/southbridge/intel/i82801xx/cmos_failover.c
@@ -26,7 +26,7 @@ static void check_cmos_failed(void)
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
- byte |= MAX_REBOOT_CNT << 4;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 08:43:38 +0000