5 files changed, 63 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index 2e9d31a3e8..31264295ad 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -15,6 +15,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
 
+bootblock-y += early_init.c
 bootblock-y += bootblock_gcc.c
 
 ramstage-y += i82801gx.c
@@ -34,6 +35,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 smm-y += smihandler.c
 
+romstage-y += early_init.c
 romstage-y += early_smbus.c
 romstage-y += early_cir.c
 
diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c
index 996788888a..063a461e43 100644
--- a/src/southbridge/intel/i82801gx/bootblock_gcc.c
+++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c
@@ -41,4 +41,6 @@ void bootblock_early_southbridge_init(void)
 
 	/* Disable watchdog timer */
 	RCBA32(GCS) = RCBA32(GCS) | 0x20;
+
+	i82801gx_lpc_setup();
 }
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 4e78c30db2..75b957573e 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -80,6 +80,12 @@ struct southbridge_intel_i82801gx_config {
 	int docking_supported:1;
 	int p_cnt_throttling_supported:1;
 	int c3_latency;
+
+	/* Additional LPC IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
new file mode 100644
index 0000000000..533aaefe14
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include "i82801gx.h"
+#include "chip.h"
+
+void i82801gx_lpc_setup(void)
+{
+	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
+	const struct device *dev = pcidev_on_root(0x1f, 0);
+	const struct southbridge_intel_i82801gx_config *config;
+
+	/* Configure serial IRQs.*/
+	pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0);
+	/*
+	 * Enable some common LPC IO ranges:
+	 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
+	 * - 0x60/0x64, 0x62/0x66 often KBC/EC
+	 * - 0x3f0-0x3f5/0x3f7 FDD
+	 * - 0x378-0x37f and 0x778-0x77f LPT
+	 * - 0x2f8-0x2ff COMB
+	 * - 0x3f8-0x3ff COMA
+	 * - 0x208-0x20f GAMEH
+	 * - 0x200-0x207 GAMEL
+	 */
+	pci_write_config16(d31f0, LPC_IO_DEC, 0x0010);
+	pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+			   | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+			   | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			   | COMB_LPC_EN | COMA_LPC_EN);
+
+	/* Set up generic decode ranges */
+	if (!dev || !dev->chip_info)
+		return;
+	config = dev->chip_info;
+
+	pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec);
+	pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec);
+	pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec);
+	pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec);
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 8c85331af9..259fb49f54 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -40,6 +40,7 @@ void i82801gx_enable(struct device *dev);
 #endif
 
 void enable_smbus(void);
+void i82801gx_lpc_setup(void);
 
 #if ENV_ROMSTAGE
 int smbus_read_byte(unsigned int device, unsigned int address);