diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/early_init.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/early_init.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/romstage.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/smbus.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 8df4a00f1b..d4ff7837b9 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -35,7 +35,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ /* Unlock registers. */ outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c index f9f31348cb..1e281aad5b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c @@ -142,7 +142,7 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c index 7ce3c7fef5..af79925479 100644 --- a/src/southbridge/intel/fsp_i89xx/early_init.c +++ b/src/southbridge/intel/fsp_i89xx/early_init.c @@ -29,7 +29,7 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index 268ea668ba..863ff6aefd 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -172,7 +172,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { /* For reference print FSP version */ uint32_t version = MCHBAR32(0x5034); printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n", - version >> 24 , (version >> 16) & 0xff, + version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (uint32_t)status); diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 3477c52c32..5b95c57d8d 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -68,7 +68,7 @@ static void pwrmgt_enable(struct device *dev) * power-on default is 0x7fffbfffh */ if (gpo) { /* only 8bit access allowed */ - outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); + outb(gpo & 0xff, DEFAULT_PMBASE + GPO0); outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); |