diff options
Diffstat (limited to 'src/southbridge/intel')
34 files changed, 101 insertions, 30 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 21816e5136..e3ad885cb4 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -56,4 +56,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index e873f55375..25dcfe0ffe 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb2), XHCI, 8, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value CBMC, 32, diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4a033abfb1..5a80ab0b3e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -181,7 +181,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 767d3ad936..6ed3dce8b9 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -218,7 +218,7 @@ void early_pch_init_native(void) static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index 969d59209b..1c33b0cd73 100644 --- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -97,7 +97,11 @@ struct __packed global_nvs { u8 rsvd11[6]; /* XHCI */ u8 xhci; - u8 rsvd12[65]; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; + u8 rsvd12[57]; u8 tpiq; /* 0xf5 - trackpad IRQ value */ u32 cbmc; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 2adfbd5c98..fe2a37c849 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -254,6 +254,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -279,9 +283,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b0226a6e9a..f5a39ecfa6 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -242,6 +242,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -268,9 +272,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index bef98fae10..28337f6913 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -186,7 +186,7 @@ void southbridge_smm_xhci_sleep(u8 slp_type) return; /* Verify that RCBA is still valid */ - if (pci_read_config32(PCH_LPC_DEV, RCBA) != ((u32)DEFAULT_RCBA | RCBA_ENABLE)) + if (pci_read_config32(PCH_LPC_DEV, RCBA) != (CONFIG_FIXED_RCBA_MMIO_BASE | RCBA_ENABLE)) return; if (RCBA32(FD) & PCH_DISABLE_XHCI) diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index a14513dead..1bdefd4b93 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -104,6 +104,14 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE +config FIXED_RCBA_MMIO_BASE + hex + default 0xfed1c000 + +config RCBA_LENGTH + hex + default 0x4000 + config FIXED_SMBUS_IO_BASE hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 712a477cc1..4a9847a32a 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -3,9 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H -#ifndef __ACPI__ - -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE) /* Root Complex Register Block */ #define RCBA 0xf0 @@ -23,10 +21,4 @@ #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) -#else - -#define DEFAULT_RCBA 0xfed1c000 - -#endif /* __ACPI__ */ - #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 1e3889b4f5..a3b15b68d7 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -101,4 +101,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 4d077205a3..6c9c9694f9 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -110,7 +110,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { // Backbone diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 72281ea5f3..c8a6117de5 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -48,7 +48,7 @@ void i82801gx_lpc_setup(void) void i82801gx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index b2a6baa7e8..933921c3f4 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -98,6 +98,10 @@ struct __packed global_nvs { u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index d2af885b0e..f408a8c53a 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -103,4 +103,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index f720505c08..1a07ec211c 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -110,7 +110,7 @@ Scope(\) // ICH9 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 3c0f3aeff4..f781098f33 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -51,7 +51,7 @@ void i82801ix_early_init(void) enable_smbus(); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 2d4980bec3..3c9aac90a2 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -98,6 +98,10 @@ struct __packed global_nvs { u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index d2af885b0e..264b52a3b0 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -103,4 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index d6136af14f..0e4c03b07a 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -112,7 +112,7 @@ Scope(\) // ICH10 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 771460955c..327c8fc0a5 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -50,7 +50,7 @@ void i82801jx_setup_bars(void) const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 4325a8c1ee..54c4a2c7c4 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -97,6 +97,10 @@ struct __packed global_nvs { u8 bten; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f172bf1eb3..34ae2f112a 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -53,4 +53,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 949da74d8c..46c6f4f958 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb2), XHCI, 8, CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378eca4..99fa5306ff 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -80,7 +80,7 @@ void bootblock_early_southbridge_init(void) /* Enable RCBA */ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index f5285c1355..2fa4b52d23 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -30,7 +30,7 @@ static void pch_default_disable(void) void ibexpeak_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index 5ce88a68b1..03897cd4b7 100644 --- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -100,6 +100,10 @@ struct __packed global_nvs { u8 xhci; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6a45fb42eb..20b8aac94a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -476,6 +476,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -494,9 +498,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 979e084161..1b06beb7b6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -93,6 +93,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer + + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc274d..50f73cdf9c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,7 +19,7 @@ Scope (\) } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58ef88..c063bfb10a 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,7 +7,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a8760c..ace8b54552 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -36,7 +36,7 @@ enum pch_platform_type get_pch_platform_type(void) static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h index 17ded13589..7db206e6e9 100644 --- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h @@ -73,6 +73,10 @@ struct __packed global_nvs { u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 24a5a7ef9a..b0ff5450cf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -557,10 +557,10 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { + if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { res = new_resource(dev, RCBA); - res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; - res->size = 16 * 1024; + res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; + res->size = CONFIG_RCBA_LENGTH; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; } |