diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/chip.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/fadt.c | 13 |
2 files changed, 3 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index ac29944070..797c93f3aa 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -63,7 +63,6 @@ struct southbridge_intel_bd82x6x_config { /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; - int c2_latency; int docking_supported; uint8_t pcie_hotplug_map[8]; diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index b0f4777d03..77af4e89b5 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; fadt->sci_int = 0x9; @@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; + /* P_LVLx not used */ + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; @@ -55,9 +51,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; |