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-rw-r--r--src/southbridge/intel/common/tco.h9
-rw-r--r--src/southbridge/intel/common/watchdog.c4
2 files changed, 4 insertions, 9 deletions
diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h
index 5bf386f1c2..b586fe5aa7 100644
--- a/src/southbridge/intel/common/tco.h
+++ b/src/southbridge/intel/common/tco.h
@@ -10,13 +10,8 @@
#undef TCO1_CNT
#endif
-#define PMBASE_TCO_OFFSET 0x60
+#include <soc/intel/common/tco.h>
-#define TCO1_STS 0x04
-#define TCO_TIMEOUT (1 << 3)
-#define TCO2_STS 0x06
-#define TCO2_STS_SECOND_TO (1 << 1)
-#define TCO1_CNT 0x08
-#define TCO_TMR_HLT (1 << 11)
+#define PMBASE_TCO_OFFSET 0x60
#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */
diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c
index 1c43a0cd9b..36b9525f13 100644
--- a/src/southbridge/intel/common/watchdog.c
+++ b/src/southbridge/intel/common/watchdog.c
@@ -27,11 +27,11 @@ void watchdog_off(void)
/* Disable the watchdog timer. */
value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
- value |= TCO_TMR_HLT;
+ value |= TCO1_TMR_HLT;
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
/* Clear TCO timeout status. */
- write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT);
+ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_STS_TIMEOUT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");