diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch_common.c | 51 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
4 files changed, 2 insertions, 55 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1396a6395b..dae3c32c86 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -29,6 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 24d7e2d24e..7ce3da70ad 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,7 +38,7 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c early_pch_common.c +romstage-y += early_spi.c romstage-y += early_rcba.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -47,6 +47,4 @@ else romstage-y += early_me_mrc.c early_usb_mrc.c endif -ramstage-y += early_pch_common.c - endif diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c deleted file mode 100644 index 2e9ad7f826..0000000000 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include "pch.h" -#include <arch/acpi.h> -#include <console/console.h> - -#if ENV_ROMSTAGE -int southbridge_detect_s3_resume(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - return 1; - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } - - return 0; -} -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 67b0d11415..741996531f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -int southbridge_detect_s3_resume(void); struct southbridge_usb_port { |