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Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/fsp_i89xx/Kconfig1
-rw-r--r--src/southbridge/intel/fsp_i89xx/pch.h9
-rw-r--r--src/southbridge/intel/fsp_i89xx/smihandler.c20
3 files changed, 13 insertions, 17 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index 359d99a9b4..9dfbbf7169 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -21,6 +21,7 @@ if SOUTHBRIDGE_INTEL_FSP_I89XX
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h
index fdc61f598d..6d8b873c3e 100644
--- a/src/southbridge/intel/fsp_i89xx/pch.h
+++ b/src/southbridge/intel/fsp_i89xx/pch.h
@@ -18,6 +18,8 @@
#ifndef SOUTHBRIDGE_INTEL_I89XX_PCH_H
#define SOUTHBRIDGE_INTEL_I89XX_PCH_H
+#include <arch/acpi.h>
+
/* PCH types */
#define PCH_TYPE_CC 0x23 /* CaveCreek */
@@ -357,13 +359,6 @@ static const struct dev_irq_regs irq_regs[NUM_IR_DEVS] = {
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index b67c393675..4943525590 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -326,24 +326,24 @@ static void southbridge_smi_sleep(void)
/* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
- slp_typ = (reg32 >> 10) & 7;
+ slp_typ = acpi_sleep_from_pm1(reg32);
/* Do any mainboard sleep handling */
- mainboard_smi_sleep(slp_typ-2);
+ mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
- if (slp_typ >= 5)
- elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+ if (slp_typ >= ACPI_S3)
+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
#endif
/* Next, do the deed.
*/
switch (slp_typ) {
- case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
- case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
- case 5:
+ case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+ case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+ case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Gate memory reset */
@@ -352,8 +352,8 @@ static void southbridge_smi_sleep(void)
/* Invalidate the cache before going to S3 */
wbinvd();
break;
- case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
- case 7:
+ case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+ case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
outl(0, pmbase + GPE0_EN);
@@ -382,7 +382,7 @@ static void southbridge_smi_sleep(void)
outl(reg32 | SLP_EN, pmbase + PM1_CNT);
/* Make sure to stop executing code here for S3/S4/S5 */
- if (slp_typ > 1)
+ if (slp_typ >= ACPI_S3)
halt();
/* In most sleep states, the code flow of this function ends at