8 files changed, 0 insertions, 18 deletions
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index 7b36583495..c7ba5c25ae 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -39,9 +39,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	}
 	fadt->p_lvl2_lat = c2_latency;
 	fadt->p_lvl3_lat = 87;
-	/* flush_* is ignored if ACPI_FADT_WBINVD is set */
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	/* P_CNT not supported */
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index c775af0c92..249b22b5bc 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
 	fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
-	fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
 	fadt->duty_width = 3; /* this width is in bits */
 	fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c
index 8be39bfdb6..b2f7d5fff8 100644
--- a/src/southbridge/intel/i82801dx/fadt.c
+++ b/src/southbridge/intel/i82801dx/fadt.c
@@ -41,8 +41,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 8;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c
index 35a1facb55..11d4aac79d 100644
--- a/src/southbridge/intel/i82801gx/fadt.c
+++ b/src/southbridge/intel/i82801gx/fadt.c
@@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 8;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = chip->c3_latency;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1;
 	if (chip->p_cnt_throttling_supported)
 		fadt->duty_width = 3;
diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c
index 710f585f8c..8ea69e8058 100644
--- a/src/southbridge/intel/i82801ix/fadt.c
+++ b/src/southbridge/intel/i82801ix/fadt.c
@@ -34,8 +34,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 16;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x39;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 3;
 	fadt->day_alrm = 0xd;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index 6f80aa6d66..ac2ba76b70 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -37,8 +37,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 16;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = chip->c3_latency;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index 103fda6ca9..93c95b5692 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -39,9 +39,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	}
 	fadt->p_lvl2_lat = c2_latency;
 	fadt->p_lvl3_lat = 87;
-	/* flush_* is ignored if ACPI_FADT_WBINVD is set */
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	/* P_CNT not supported */
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c
index 7c1bef9941..2868b5f943 100644
--- a/src/southbridge/intel/lynxpoint/fadt.c
+++ b/src/southbridge/intel/lynxpoint/fadt.c
@@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;