diff options
Diffstat (limited to 'src/southbridge/intel/sch')
| -rw-r--r-- | src/southbridge/intel/sch/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/sch/usb_debug.c | 47 |
2 files changed, 0 insertions, 48 deletions
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 9821fedc33..b321a6c4ca 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -33,7 +33,6 @@ ramstage-y += reset.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c deleted file mode 100644 index fb436b5af7..0000000000 --- a/src/southbridge/intel/sch/usb_debug.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <console/console.h> -#include <usbdebug.h> -#include <device/pci_def.h> - -/* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) -{ - /* Not needed, the southbridges hardcode physical USB port 1. */ -} - -void enable_usbdebug(unsigned int port) -{ - u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ - - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - - /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); - dbgctl |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); -} |