diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/finalize.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 18 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pmutil.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smi.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smihandler.c | 10 |
9 files changed, 28 insertions, 28 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index c30bfa47dd..fbbd26d66f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -96,7 +96,7 @@ Scope(\) #include "smbus.asl" // Serial IO -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "serialio.asl" #include "lpt_lp.asl" #endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 0e4fa3d5ea..cb4bc7efb6 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -24,7 +24,7 @@ #include "pch.h" #include "chip.h" -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else #include "southbridge/intel/common/gpio.h" @@ -133,7 +133,7 @@ int early_pch_init(const void *gpio_map, pch_enable_bars(); -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) setup_pch_lp_gpios(gpio_map); #else setup_pch_gpios(gpio_map); @@ -154,7 +154,7 @@ int early_pch_init(const void *gpio_map, wake_from_s3 = sleep_type_s3(); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (!wake_from_s3) boot_count_increment(); #endif diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 79a0915671..e95872be3c 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -34,7 +34,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff78ea9eeb..b43ca329b6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -77,7 +77,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -292,7 +292,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -498,7 +498,7 @@ static void enable_lp_clock_gating(device_t dev) static void pch_set_acpi_mode(void) { -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -760,7 +760,7 @@ static void southbridge_inject_dsdt(device_t dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 355db4b6e1..c393feb377 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -37,7 +37,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -59,7 +59,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); static u32 *mei_base_address; void intel_me_mbp_clear(device_t dev); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -519,7 +519,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) #endif /* CONFIG_DEBUG_INTEL_ME */ #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -579,7 +579,7 @@ void intel_me_finalize_smm(void) if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if CONFIG_ME_MBP_CLEAR_LATE +#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); #endif @@ -707,7 +707,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -796,7 +796,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -835,7 +835,7 @@ static void intel_me_init(device_t dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) me_print_fwcaps(mbp_data.fw_capabilities); #endif @@ -991,7 +991,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) host.interrupt_generate = 1; write_host_csr(&host); -#if !CONFIG_ME_MBP_CLEAR_LATE +#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for the mbp_cleared indicator. */ intel_me_mbp_clear(dev); #endif @@ -1000,7 +1000,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 655aef1353..c9c9c32acd 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -72,7 +72,7 @@ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #define DEFAULT_PMBASE 0x1000 #define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 @@ -181,7 +181,7 @@ void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index d895c56df1..b14c1f7c91 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "pch.h" -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #endif diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 8c9cb58cbf..5f1bdf76fa 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -29,7 +29,7 @@ void southbridge_smm_clear_state(void) { u32 smi_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif @@ -123,7 +123,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) /* * Finalize system before payload boot if not in ChromeOS environment. */ -#if !CONFIG_CHROMEOS +#if !IS_ENABLED(CONFIG_CHROMEOS) static void finalize_boot(void *unused) { diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 0102308812..37a7a2b6a7 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -130,13 +130,13 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ); /* USB sleep preparations */ -#if !CONFIG_FINALIZE_USB_ROUTE_XHCI +#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI) usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); #endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -243,7 +243,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -314,7 +314,7 @@ static void southbridge_smi_apmc(void) case 0xca: usb_xhci_route_all(); break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -333,7 +333,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); |