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-rw-r--r--src/southbridge/intel/lynxpoint/acpi/pch.asl2
-rw-r--r--src/southbridge/intel/lynxpoint/bootblock.c2
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c4
4 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index a878dc274d..f97a5ad58d 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -19,7 +19,7 @@ Scope (\)
}
// Root Complex Register Block
- OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
+ OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Field (RCRB, DWordAcc, Lock, Preserve)
{
Offset (0x3404), // High Performance Timer Configuration
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 802c58ef88..c063bfb10a 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -7,7 +7,7 @@
static void map_rcba(void)
{
- pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+ pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
}
static void enable_port80_on_lpc(void)
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 8cc6a8760c..ace8b54552 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -36,7 +36,7 @@ enum pch_platform_type get_pch_platform_type(void)
static void pch_enable_bars(void)
{
- pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+ pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 24a5a7ef9a..20b9b4318f 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -557,9 +557,9 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */
- if ((uintptr_t)DEFAULT_RCBA < default_decode_base) {
+ if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) {
res = new_resource(dev, RCBA);
- res->base = (resource_t)(uintptr_t)DEFAULT_RCBA;
+ res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE;
res->size = 16 * 1024;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE;