5 files changed, 15 insertions, 18 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c
index c4ea418ade..cfdcee6896 100644
--- a/src/southbridge/intel/lynxpoint/acpi.c
+++ b/src/southbridge/intel/lynxpoint/acpi.c
@@ -41,7 +41,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
 }
 
-static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs)
+static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs)
 {
 	char sio_name[5] = {};
 	snprintf(sio_name, sizeof(sio_name), "S%1uEN", id);
@@ -51,7 +51,7 @@ static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs)
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
 {
 	unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
-	global_nvs_t *gnvs = acpi_get_gnvs();
+	struct global_nvs *gnvs = acpi_get_gnvs();
 	int id;
 
 	if (!gnvs)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 78536f6c10..f486434045 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -11,6 +11,7 @@
 #include <arch/io.h>
 #include <arch/ioapic.h>
 #include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
 #include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <string.h>
@@ -669,7 +670,7 @@ static void pch_lpc_add_io_resources(struct device *dev)
 
 static void pch_lpc_read_resources(struct device *dev)
 {
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
 	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
@@ -681,9 +682,9 @@ static void pch_lpc_read_resources(struct device *dev)
 	pch_lpc_add_io_resources(dev);
 
 	/* Allocate ACPI NVS in CBMEM */
-	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
 	if (!acpi_is_wakeup_s3() && gnvs)
-		memset(gnvs, 0, sizeof(global_nvs_t));
+		memset(gnvs, 0, sizeof(struct global_nvs));
 }
 
 static void pch_lpc_enable(struct device *dev)
@@ -695,9 +696,9 @@ static void pch_lpc_enable(struct device *dev)
 	pch_enable(dev);
 }
 
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
 {
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
 	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 	if (!gnvs) {
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index b5b6e9fc02..4abe026354 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -4,7 +4,7 @@
 #include <stdint.h>
 #include "vendorcode/google/chromeos/gnvs.h"
 
-typedef struct global_nvs_t {
+struct __packed global_nvs {
 	/* Miscellaneous */
 	u16	osys; /* 0x00 - Operating System */
 	u8	smif; /* 0x02 - SMI function call ("TRAP") */
@@ -76,10 +76,6 @@ typedef struct global_nvs_t {
 
 	/* ChromeOS specific (starts at 0x100)*/
 	chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
 
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-
-void acpi_create_gnvs(global_nvs_t * gnvs);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 3973a8d94a..77da5351ad 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -205,7 +205,7 @@ static void serialio_init(struct device *dev)
 	}
 
 	if (config->sio_acpi_mode) {
-		global_nvs_t *gnvs;
+		struct global_nvs *gnvs;
 
 		/* Find ACPI NVS to update BARs */
 		gnvs = acpi_get_gnvs();
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index be842c5720..0bc1e2a86f 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -24,8 +24,8 @@ static u8 smm_initialized = 0;
 /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
  * by coreboot.
  */
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
 {
 	return gnvs;
 }
@@ -325,7 +325,7 @@ static void southbridge_smi_apmc(void)
 		state = smi_apmc_find_state_save(reg8);
 		if (state) {
 			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (global_nvs_t *)((u32)state->rbx);
+			gnvs = (struct global_nvs *)((u32)state->rbx);
 			smm_initialized = 1;
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}