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-rw-r--r--src/southbridge/intel/lynxpoint/azalia.c10
-rw-r--r--src/southbridge/intel/lynxpoint/bootblock.c2
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c2
-rw-r--r--src/southbridge/intel/lynxpoint/hda_verb.c12
-rw-r--r--src/southbridge/intel/lynxpoint/hda_verb.h6
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c12
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c18
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c16
-rw-r--r--src/southbridge/intel/lynxpoint/serialio.c32
-rw-r--r--src/southbridge/intel/lynxpoint/usb_ehci.c8
-rw-r--r--src/southbridge/intel/lynxpoint/usb_xhci.c22
12 files changed, 74 insertions, 70 deletions
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index be056be493..168b8d22a2 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -30,7 +30,7 @@
#include "pch.h"
#include "hda_verb.h"
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
@@ -46,7 +46,7 @@ static void codecs_init(u32 base, u32 codec_mask)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
-static void azalia_pch_init(struct device *dev, u32 base)
+static void azalia_pch_init(struct device *dev, u8 *base)
{
u8 reg8;
u16 reg16;
@@ -131,7 +131,7 @@ static void azalia_pch_init(struct device *dev, u32 base)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -141,8 +141,8 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 40c6bb8c46..9d9e7b3a8c 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -53,7 +53,7 @@ static void map_rcba(void)
{
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
- pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
}
static void enable_port80_on_lpc(void)
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 5378428e83..eabf548d7a 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -52,7 +52,7 @@ int pch_is_lp(void)
static void pch_enable_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
- pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 424deb52bb..8f38ccec60 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -28,7 +28,7 @@
/**
* Set bits in a register and wait for status
*/
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -60,7 +60,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
/**
* Probe for supported codecs
*/
-int hda_codec_detect(u32 base)
+int hda_codec_detect(u8 *base)
{
u8 reg8;
@@ -91,7 +91,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int hda_wait_for_ready(u32 base)
+static int hda_wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -113,7 +113,7 @@ static int hda_wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int hda_wait_for_valid(u32 base)
+static int hda_wait_for_valid(u8 *base)
{
u32 reg32;
@@ -185,7 +185,7 @@ static u32 hda_find_verb(u32 verb_table_bytes,
/**
* Write a supplied verb table
*/
-int hda_codec_write(u32 base, u32 size, const u32 *data)
+int hda_codec_write(u8 *base, u32 size, const u32 *data)
{
int i;
@@ -205,7 +205,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
/**
* Initialize codec, then find the verb table and write it
*/
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h
index 8b3d27e1c2..52c1468c06 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.h
+++ b/src/southbridge/intel/lynxpoint/hda_verb.h
@@ -30,8 +30,8 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-int hda_codec_detect(u32 base);
-int hda_codec_write(u32 base, u32 size, const u32 *data);
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
+int hda_codec_detect(u8 *base);
+int hda_codec_write(u8 *base, u32 size, const u32 *data);
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data);
#endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 563cb0a26d..d753bea776 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -57,22 +57,22 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
if (pch_is_lp()) {
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
}
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
@@ -608,9 +608,9 @@ static void pch_lpc_add_mmio_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */
- if (DEFAULT_RCBA < default_decode_base) {
+ if ((uintptr_t)DEFAULT_RCBA < default_decode_base) {
res = new_resource(dev, RCBA);
- res->base = DEFAULT_RCBA;
+ res->base = (resource_t)(uintptr_t)DEFAULT_RCBA;
res->size = 16 * 1024;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE;
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 9670bbb659..e32a2d9be3 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
#if CONFIG_DEBUG_INTEL_ME
@@ -104,7 +104,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -113,7 +113,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -141,13 +141,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -577,11 +577,11 @@ void intel_me_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
#if CONFIG_ME_MBP_CLEAR_LATE
@@ -745,7 +745,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 9b5cb6f160..5ee7cd973b 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -83,7 +83,11 @@
#endif
#define HPET_ADDR 0xfed00000
+#ifndef __ACPI__
+#define DEFAULT_RCBA ((u8 *)0xfed1c000)
+#else
#define DEFAULT_RCBA 0xfed1c000
+#endif
#ifndef __ACPI__
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 43a99c8b66..89a72f4fcc 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
} else if(config->sata_ahci) {
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -156,8 +156,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
@@ -166,11 +166,11 @@ static void sata_init(struct device *dev)
reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(abar + 0x03, config->sata_port_map);
+ (void) read32(abar + 0x03); /* Read back 1 */
+ (void) read32(abar + 0x03); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32(abar + 0x09);
/* Enable DEVSLP */
if (pch_is_lp()) {
if (config->sata_devslp_disable)
@@ -180,7 +180,7 @@ static void sata_init(struct device *dev)
} else {
reg32 &= ~0x00000002;
}
- write32(abar + 0x24, reg32);
+ write32(abar + 0x09, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 75edf5c9db..398895a2e9 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -32,9 +32,9 @@
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+ u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
reg32 |= SIO_REG_PPR_CLOCK_EN;
- write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+ write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -85,22 +85,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
- reg = read32(bar0->base + SIO_REG_PPR_GEN);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_PPR_GEN, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
/* 2. Program BAR0 + 804h[1:0] = 00b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg &= ~SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 3. Program BAR0 + 804h[1:0] = 11b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg |= SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
- write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+ write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -109,26 +109,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
/* Program BAR0 + 1010h = 0x00000000 */
- write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
/* Program BAR0 + 3Ch[30] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
- write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+ u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
- write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+ write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 845129f7b2..7c35e673e8 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -64,13 +64,13 @@ void usb_ehci_disable(device_t dev)
void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
{
u32 reg32;
- u32 bar0_base;
+ u8 *bar0_base;
u16 pwr_state;
u16 pci_cmd;
/* Check if the controller is disabled or not present */
- bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- if (bar0_base == 0 || bar0_base == 0xffffffff)
+ bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff)
return;
pci_cmd = pci_read_config32(dev, PCI_COMMAND);
@@ -86,7 +86,7 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
/* Make sure memory bar is set */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base);
/* Make sure memory space is enabled */
pci_write_config16(dev, PCI_COMMAND, pci_cmd |
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 6c7bf046a8..3b8c23b27a 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -28,7 +28,7 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
-static u32 usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -36,7 +36,7 @@ static u32 usb_xhci_mem_base(device_t dev)
if (mem_base == 0 || mem_base == 0xffffffff)
return 0;
- return mem_base & ~0xf;
+ return (u8 *)(mem_base & ~0xf);
}
static int usb_xhci_port_count_usb3(device_t dev)
@@ -46,7 +46,7 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 4;
} else {
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
u32 fus = read32(mem_base + XHCI_USB3FUS);
fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK;
@@ -60,9 +60,9 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 0;
}
-static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
@@ -71,9 +71,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
write32(portsc, status);
}
-static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
@@ -92,7 +92,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
@@ -121,7 +121,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
@@ -164,7 +164,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
return;
@@ -295,7 +295,7 @@ static void usb_xhci_init(device_t dev)
{
u32 reg32;
u16 reg16;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 21:11:06 +0000