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Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c3
2 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 465aa1e710..8cc6a8760c 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -40,7 +40,7 @@ static void pch_enable_bars(void)
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
- pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
+ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 2872a0b556..2db4b59006 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -41,9 +41,6 @@ static void pch_enable_ioapic(struct device *dev)
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */
- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */