diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 61 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 46 |
2 files changed, 8 insertions, 99 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2747b21cf9..2c71ab2a53 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH + select HAVE_INTEL_FIRMWARE + select USES_INTEL_ME config INTEL_LYNXPOINT_LP bool @@ -59,60 +61,20 @@ config HAVE_IFD_BIN default y config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" + bool default y if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (ifd.bin) for your - board, you can select this option and coreboot will build without it. - Though, the resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_GBE_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" config IFD_BIN_PATH - string "Path to intel firmware descriptor" + string depends on !BUILD_WITH_FAKE_IFD default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" + bool default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. config ME_BIN_PATH - string "Path to management engine firmware" + string depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" @@ -133,16 +95,7 @@ config FINALIZE_USB_ROUTE_XHCI to the XHCI controller during the finalize SMM callback. config LOCK_MANAGEMENT_ENGINE - bool "Lock Management Engine section" + bool default n - help - The Intel Management Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. endif diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index a22251afc0..a42fe3946f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -19,10 +19,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -INTERMEDIATE:=lynxpoint_add_me +subdirs-y += ../common/firmware ramstage-y += pch.c ramstage-y += azalia.c @@ -66,45 +63,4 @@ ramstage-y += gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c endif -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -endif - -lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(CONFIG_ME_BIN_PATH) \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -PHONY += lynxpoint_add_me - endif |