diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 8632ad849e..ce8f0e0e81 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -23,6 +23,16 @@ Scope(\) { + // Return TRUE if chipset is LynxPoint-LP + Method (ISLP, 0, NotSerialized) + { + If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) { + Return (1) + } else { + Return (0) + } + } + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. OperationRegion(IO_T, SystemIO, 0x800, 0x10) @@ -33,7 +43,7 @@ Scope(\) } // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff) Field(PMIO, ByteAcc, NoLock, Preserve) { Offset(0x20), // GPE0_STS |