diff options
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/globalnvs.asl | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/bootblock.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/include/soc/nvs.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/me.c | 7 |
6 files changed, 23 insertions, 3 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f172bf1eb3..34ae2f112a 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -53,4 +53,12 @@ config HPET_MIN_TICKS hex default 0x80 +config HIDE_MEI_ON_ERROR + bool "Hide MEI device on error" + default n + help + If you enable this option, the Management Engine Interface + device will be hidden when ME is in an inoperable mode, e.g. + if me_cleaner was used. + endif diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 949da74d8c..46c6f4f958 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb2), XHCI, 8, CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378eca4..99fa5306ff 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -80,7 +80,7 @@ void bootblock_early_southbridge_init(void) /* Enable RCBA */ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index f5285c1355..2fa4b52d23 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -30,7 +30,7 @@ static void pch_default_disable(void) void ibexpeak_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index 5ce88a68b1..03897cd4b7 100644 --- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -100,6 +100,10 @@ struct __packed global_nvs { u8 xhci; u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; }; #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 6a45fb42eb..20b8aac94a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -476,6 +476,10 @@ static void intel_me_init(struct device *dev) switch (path) { case ME_S3WAKE_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: +#if CONFIG(HIDE_MEI_ON_ERROR) + case ME_ERROR_BIOS_PATH: +#endif intel_me_hide(dev); break; @@ -494,9 +498,10 @@ static void intel_me_init(struct device *dev) */ break; +#if !CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: +#endif case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: break; } |