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Diffstat (limited to 'src/southbridge/intel/ibexpeak')
-rw-r--r--src/southbridge/intel/ibexpeak/azalia.c4
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/sata.c2
-rw-r--r--src/southbridge/intel/ibexpeak/smbus.h8
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c64
5 files changed, 40 insertions, 40 deletions
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index dfcbcb60a6..d9f635a925 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -115,7 +115,7 @@ static int wait_for_ready(u8 *base)
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -143,7 +143,7 @@ static int wait_for_valid(u8 *base)
/* Use a 1msec timeout */
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 88ec851582..23b192575f 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -120,7 +120,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index e7681fb3cb..19ef098808 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -126,7 +126,7 @@ static void sata_init(struct device *dev)
reg32 &= ~0x00000005;
write32(abar + 0x28, reg32);
} else {
- /* IDE */
+ /* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */
diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h
index aeac5732ab..0815bf4f14 100644
--- a/src/southbridge/intel/ibexpeak/smbus.h
+++ b/src/southbridge/intel/ibexpeak/smbus.h
@@ -171,7 +171,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -184,7 +184,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb(*buf++, smbus_base + SMBBLKDAT);
outb(status, smbus_base + SMBHSTSTAT);
}
- } while(status & 0x01);
+ } while (status & 0x01);
return 0;
}
@@ -214,7 +214,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -234,7 +234,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
smbus_base + SMBHSTCTL);
}
}
- } while(status & 0x01);
+ } while (status & 0x01);
return bytes_read;
}
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d11d531777..0ad7e658fc 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
static void southbridge_gate_memory_reset_real(int offset,
@@ -849,7 +849,7 @@ void southbridge_smi_handler(void)
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 02:50:28 +0000