diff options
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.h')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 34f80330bc..556b9e0a0b 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -66,6 +66,26 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type); +enum current_lookup_idx { + IF1_F57 = 0, + IF1_F5F, + IF1_753, + IF1_75F, + IF1_14B, + IF1_74B, + IF1_557, + IF1_757, + IF1_55F, + IF1_54B, +}; + +struct southbridge_usb_port { + int enabled; + enum current_lookup_idx current; + int oc_pin; +}; +void early_usb_init(const struct southbridge_usb_port *portmap); + #ifndef __ROMCC__ #include <device/device.h> void pch_enable(struct device *dev); @@ -75,6 +95,10 @@ void pch_enable(struct device *dev); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -401,6 +425,36 @@ void pch_enable(struct device *dev); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) +/* USB Initialization Registers[13:0] */ +#define USBIR0 0x3500 /* 32bit */ +#define USBIR1 0x3504 /* 32bit */ +#define USBIR2 0x3508 /* 32bit */ +#define USBIR3 0x350c /* 32bit */ +#define USBIR4 0x3510 /* 32bit */ +#define USBIR5 0x3514 /* 32bit */ +#define USBIR6 0x3518 /* 32bit */ +#define USBIR7 0x351c /* 32bit */ +#define USBIR8 0x3520 /* 32bit */ +#define USBIR9 0x3524 /* 32bit */ +#define USBIR10 0x3528 /* 32bit */ +#define USBIR11 0x352c /* 32bit */ +#define USBIR12 0x3530 /* 32bit */ +#define USBIR13 0x3534 /* 32bit */ + +#define USBIRC 0x3564 /* 32bit */ +#define USBIRA 0x3570 /* 32bit */ +#define USBIRB 0x357c /* 32bit */ + +/* Miscellaneous Control Register */ +#define MISCCTL 0x3590 /* 32bit */ +/* USB Port Disable Override */ +#define USBPDO 0x359c /* 32bit */ +/* USB Overcurrent MAP Register */ +#define USBOCM1 0x35a0 /* 32bit */ +#define USBOCM2 0x35a4 /* 32bit */ +/* Rate Matching Hub Wake Control Register */ +#define RMHWKCTL 0x35b0 /* 32bit */ + /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) |