diff options
Diffstat (limited to 'src/southbridge/intel/ibexpeak/lpc.c')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index bd12944adf..7d025cc3b5 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -100,9 +100,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Interrupt 11 is not used by legacy devices and so can always be used for PCI interrupts. Full legacy IRQ routing is complicated and hard to get right. Fortunately all modern OS use MSI and so it's not that big of @@ -137,7 +137,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -166,7 +166,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, GPIO_ROUT, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -394,7 +394,7 @@ static void enable_hpet(void) write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } -static void enable_clock_gating(device_t dev) +static void enable_clock_gating(struct device *dev) { u32 reg32; u16 reg16; @@ -532,7 +532,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -593,13 +593,13 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ RCBA16(DISPBDF) = 0x0010; @@ -608,7 +608,8 @@ static void pch_lpc_enable(device_t dev) pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -619,7 +620,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -647,7 +648,7 @@ static void southbridge_inject_dsdt(device_t dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; @@ -781,9 +782,9 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(device_t device) +static void southbridge_fill_ssdt(struct device *device) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); |