diff options
Diffstat (limited to 'src/southbridge/intel/ibexpeak/early_pch.c')
-rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ccd8f74431..b76115bf84 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -22,45 +22,6 @@ #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> -#include "chip.h" - -static void early_lpc_init(void) -{ - const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_ibexpeak_config *config = NULL; - - /* Add some default decode ranges: - - 0x2e/2f, 0x4e/0x4f - - EC/Mouse/KBC 60/64, 62/66 - - 0x3f8 COMA - If more are needed, update in mainboard_lpc_init hook - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - /* Clear PWR_FLR */ - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); - - /* Set up generic decode ranges */ - if (!dev) - return; - if (dev->chip_info) - config = dev->chip_info; - if (!config) - return; - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); -} - static void early_gpio_init(void) { pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); @@ -80,12 +41,6 @@ static void pch_default_disable(void) RCBA32(FD2) = 1; } -void pch_pre_console_init(void) -{ - early_lpc_init(); - mainboard_lpc_init(); -} - void early_pch_init(void) { early_gpio_init(); |